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Commit a4efb090 authored by Stephen Boyd's avatar Stephen Boyd
Browse files

Merge tag 'clk-renesas-for-v4.10-tag1' of... 

Merge tag 'clk-renesas-for-v4.10-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next

Pull Renesas clk driver updates from Geert Uytterhoeven:

  - SYS-DMAC, (H)SCIF, I2C, DRIF, and graphics related clocks for R-Car
    M3-W,
  - Minor fixes and cleanups.

* tag 'clk-renesas-for-v4.10-tag1' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers:
  clk: renesas: r8a7796: Add DU and LVDS clocks
  clk: renesas: r8a7796: Add VSP clocks
  clk: renesas: r8a7796: Add FCP clocks
  clk: renesas: cpg-mssr: Remove bogus commas from error messages
  clk: renesas: r8a7796: Add DRIF clock
  clk: renesas: cpg-mssr: Fix inverted debug check
  clk: renesas: rcar-gen3-cpg: Always use readl()/writel()
  clk: renesas: cpg-mssr: Always use readl()/writel()
  clk: renesas: r8a7796: Add I2C clocks
  clk: renesas: r8a7796: Add HSCIF clocks
  clk: renesas: r8a7796: Add SCIF clocks
  clk: renesas: r8a7796: Add SYS-DMAC clocks
parents c60df0a4 dbdcc4f9

drivers/clk/renesas/r8a7796-cpg-mssr.c

+45 −0
Original line number Diff line number Diff line
@@ -109,6 +109,14 @@ static const struct cpg_core_clk r8a7796_core_clks[] __initconst = { 
};



static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = {

	DEF_MOD("scif5",		 202,	R8A7796_CLK_S3D4),

	DEF_MOD("scif4",		 203,	R8A7796_CLK_S3D4),

	DEF_MOD("scif3",		 204,	R8A7796_CLK_S3D4),

	DEF_MOD("scif1",		 206,	R8A7796_CLK_S3D4),

	DEF_MOD("scif0",		 207,	R8A7796_CLK_S3D4),

	DEF_MOD("sys-dmac2",		 217,	R8A7796_CLK_S0D3),

	DEF_MOD("sys-dmac1",		 218,	R8A7796_CLK_S0D3),

	DEF_MOD("sys-dmac0",		 219,	R8A7796_CLK_S0D3),

	DEF_MOD("cmt3",			 300,	R8A7796_CLK_R),

	DEF_MOD("cmt2",			 301,	R8A7796_CLK_R),

	DEF_MOD("cmt1",			 302,	R8A7796_CLK_R),
@@ -120,7 +128,37 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = { 
	DEF_MOD("sdif0",		 314,	R8A7796_CLK_SD0),

	DEF_MOD("rwdt0",		 402,	R8A7796_CLK_R),

	DEF_MOD("intc-ap",		 408,	R8A7796_CLK_S3D1),

	DEF_MOD("drif7",		 508,	R8A7796_CLK_S3D2),

	DEF_MOD("drif6",		 509,	R8A7796_CLK_S3D2),

	DEF_MOD("drif5",		 510,	R8A7796_CLK_S3D2),

	DEF_MOD("drif4",		 511,	R8A7796_CLK_S3D2),

	DEF_MOD("drif3",		 512,	R8A7796_CLK_S3D2),

	DEF_MOD("drif2",		 513,	R8A7796_CLK_S3D2),

	DEF_MOD("drif1",		 514,	R8A7796_CLK_S3D2),

	DEF_MOD("drif0",		 515,	R8A7796_CLK_S3D2),

	DEF_MOD("hscif4",		 516,	R8A7796_CLK_S3D1),

	DEF_MOD("hscif3",		 517,	R8A7796_CLK_S3D1),

	DEF_MOD("hscif2",		 518,	R8A7796_CLK_S3D1),

	DEF_MOD("hscif1",		 519,	R8A7796_CLK_S3D1),

	DEF_MOD("hscif0",		 520,	R8A7796_CLK_S3D1),

	DEF_MOD("thermal",		 522,	R8A7796_CLK_CP),

	DEF_MOD("fcpvd2",		 601,	R8A7796_CLK_S0D2),

	DEF_MOD("fcpvd1",		 602,	R8A7796_CLK_S0D2),

	DEF_MOD("fcpvd0",		 603,	R8A7796_CLK_S0D2),

	DEF_MOD("fcpvb0",		 607,	R8A7796_CLK_S0D1),

	DEF_MOD("fcpvi0",		 611,	R8A7796_CLK_S0D1),

	DEF_MOD("fcpf0",		 615,	R8A7796_CLK_S0D1),

	DEF_MOD("fcpci0",		 617,	R8A7796_CLK_S0D2),

	DEF_MOD("fcpcs",		 619,	R8A7796_CLK_S0D2),

	DEF_MOD("vspd2",		 621,	R8A7796_CLK_S0D2),

	DEF_MOD("vspd1",		 622,	R8A7796_CLK_S0D2),

	DEF_MOD("vspd0",		 623,	R8A7796_CLK_S0D2),

	DEF_MOD("vspb",			 626,	R8A7796_CLK_S0D1),

	DEF_MOD("vspi0",		 631,	R8A7796_CLK_S0D1),

	DEF_MOD("du2",			 722,	R8A7796_CLK_S2D1),

	DEF_MOD("du1",			 723,	R8A7796_CLK_S2D1),

	DEF_MOD("du0",			 724,	R8A7796_CLK_S2D1),

	DEF_MOD("lvds",			 727,	R8A7796_CLK_S2D1),

	DEF_MOD("etheravb",		 812,	R8A7796_CLK_S0D6),

	DEF_MOD("gpio7",		 905,	R8A7796_CLK_S3D4),

	DEF_MOD("gpio6",		 906,	R8A7796_CLK_S3D4),
@@ -130,6 +168,13 @@ static const struct mssr_mod_clk r8a7796_mod_clks[] __initconst = { 
	DEF_MOD("gpio2",		 910,	R8A7796_CLK_S3D4),

	DEF_MOD("gpio1",		 911,	R8A7796_CLK_S3D4),

	DEF_MOD("gpio0",		 912,	R8A7796_CLK_S3D4),

	DEF_MOD("i2c6",			 918,	R8A7796_CLK_S0D6),

	DEF_MOD("i2c5",			 919,	R8A7796_CLK_S0D6),

	DEF_MOD("i2c4",			 927,	R8A7796_CLK_S0D6),

	DEF_MOD("i2c3",			 928,	R8A7796_CLK_S0D6),

	DEF_MOD("i2c2",			 929,	R8A7796_CLK_S3D2),

	DEF_MOD("i2c1",			 930,	R8A7796_CLK_S3D2),

	DEF_MOD("i2c0",			 931,	R8A7796_CLK_S3D2),

};



static const unsigned int r8a7796_crit_mod_clks[] __initconst = {

drivers/clk/renesas/rcar-gen3-cpg.c

+7 −7
Original line number Diff line number Diff line
@@ -98,7 +98,7 @@ static int cpg_sd_clock_enable(struct clk_hw *hw) 
	u32 val, sd_fc;

	unsigned int i;



	val = clk_readl(clock->reg);

	val = readl(clock->reg);



	sd_fc = val & CPG_SD_FC_MASK;

	for (i = 0; i < clock->div_num; i++)
@@ -111,7 +111,7 @@ static int cpg_sd_clock_enable(struct clk_hw *hw) 
	val &= ~(CPG_SD_STP_MASK);

	val |= clock->div_table[i].val & CPG_SD_STP_MASK;



	clk_writel(val, clock->reg);

	writel(val, clock->reg);



	return 0;

}
@@ -120,14 +120,14 @@ static void cpg_sd_clock_disable(struct clk_hw *hw) 
{

	struct sd_clock *clock = to_sd_clock(hw);



	clk_writel(clk_readl(clock->reg) | CPG_SD_STP_MASK, clock->reg);

	writel(readl(clock->reg) | CPG_SD_STP_MASK, clock->reg);

}



static int cpg_sd_clock_is_enabled(struct clk_hw *hw)

{

	struct sd_clock *clock = to_sd_clock(hw);



	return !(clk_readl(clock->reg) & CPG_SD_STP_MASK);

	return !(readl(clock->reg) & CPG_SD_STP_MASK);

}



static unsigned long cpg_sd_clock_recalc_rate(struct clk_hw *hw,
@@ -138,7 +138,7 @@ static unsigned long cpg_sd_clock_recalc_rate(struct clk_hw *hw, 
	u32 val, sd_fc;

	unsigned int i;



	val = clk_readl(clock->reg);

	val = readl(clock->reg);



	sd_fc = val & CPG_SD_FC_MASK;

	for (i = 0; i < clock->div_num; i++)
@@ -189,10 +189,10 @@ static int cpg_sd_clock_set_rate(struct clk_hw *hw, unsigned long rate, 
	if (i >= clock->div_num)

		return -EINVAL;



	val = clk_readl(clock->reg);

	val = readl(clock->reg);

	val &= ~(CPG_SD_STP_MASK | CPG_SD_FC_MASK);

	val |= clock->div_table[i].val & (CPG_SD_STP_MASK | CPG_SD_FC_MASK);

	clk_writel(val, clock->reg);

	writel(val, clock->reg);



	return 0;

}

drivers/clk/renesas/renesas-cpg-mssr.c

+6 −7
Original line number Diff line number Diff line
@@ -146,12 +146,12 @@ static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable) 
		enable ? "ON" : "OFF");

	spin_lock_irqsave(&priv->mstp_lock, flags);



	value = clk_readl(priv->base + SMSTPCR(reg));

	value = readl(priv->base + SMSTPCR(reg));

	if (enable)

		value &= ~bitmask;

	else

		value |= bitmask;

	clk_writel(value, priv->base + SMSTPCR(reg));

	writel(value, priv->base + SMSTPCR(reg));



	spin_unlock_irqrestore(&priv->mstp_lock, flags);
@@ -159,8 +159,7 @@ static int cpg_mstp_clock_endisable(struct clk_hw *hw, bool enable) 
		return 0;



	for (i = 1000; i > 0; --i) {

		if (!(clk_readl(priv->base + MSTPSR(reg)) &

		      bitmask))

		if (!(readl(priv->base + MSTPSR(reg)) & bitmask))

			break;

		cpu_relax();

	}
@@ -190,7 +189,7 @@ static int cpg_mstp_clock_is_enabled(struct clk_hw *hw) 
	struct cpg_mssr_priv *priv = clock->priv;

	u32 value;



	value = clk_readl(priv->base + MSTPSR(clock->index / 32));

	value = readl(priv->base + MSTPSR(clock->index / 32));



	return !(value & BIT(clock->index % 32));

}
@@ -309,7 +308,7 @@ static void __init cpg_mssr_register_core_clk(const struct cpg_core_clk *core, 
	return;



fail:

	dev_err(dev, "Failed to register %s clock %s: %ld\n", "core,",

	dev_err(dev, "Failed to register %s clock %s: %ld\n", "core",

		core->name, PTR_ERR(clk));

}
@@ -377,7 +376,7 @@ static void __init cpg_mssr_register_mod_clk(const struct mssr_mod_clk *mod, 
	return;



fail:

	dev_err(dev, "Failed to register %s clock %s: %ld\n", "module,",

	dev_err(dev, "Failed to register %s clock %s: %ld\n", "module",

		mod->name, PTR_ERR(clk));

	kfree(clock);

}