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Commit 98f80446 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Update NPU CC clock node for SDMMAGPIE"

parents 2ba326ed 75dc7621

Documentation/devicetree/bindings/clock/qcom,npucc.txt

+2 −1
Original line number Diff line number Diff line
@@ -2,7 +2,8 @@ Qualcomm Technologies, Inc. NPU Clock & Reset Controller Binding 
----------------------------------------------------------------



Required properties :

- compatible : must contain "qcom,npucc-sm8150" or "qcom,npucc-sm8150-v2".

- compatible : must contain "qcom,npucc-sm8150" or "qcom,npucc-sm8150-v2"

		or "qcom,npucc-sdmmagpie".

- reg : shall contain base register location and length.

- reg-names: names of registers listed in the same order as in

	     the reg property.

arch/arm64/boot/dts/qcom/sdmmagpie-gdsc.dtsi

+1 −1
Original line number Diff line number Diff line
@@ -218,7 +218,7 @@ 


	/* GDSCs in NPU CC */

	npu_core_gdsc: qcom,gdsc@9911028 {

		compatible = "regulator-fixed";

		compatible = "qcom,gdsc";

		regulator-name = "npu_core_gdsc";

		reg = <0x9911028 0x4>;

		status = "disabled";

arch/arm64/boot/dts/qcom/sdmmagpie.dtsi

+7 −2
Original line number Diff line number Diff line
@@ -684,8 +684,11 @@ 
	};



	clock_npucc: qcom,npucc {

		compatible = "qcom,dummycc";

		clock-output-names = "npucc_clocks";

		compatible = "qcom,npucc-sdmmagpie", "syscon";

		reg = <0x9910000 0x10000>;

		reg-names = "cc_base";

		vdd_cx-supply = <&VDD_CX_LEVEL>;

		npu_gdsc-supply = <&npu_core_gdsc>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};
@@ -1791,6 +1794,8 @@ 
};



&npu_core_gdsc {

	clock-names = "ahb_clk";

	clocks = <&clock_gcc GCC_NPU_CFG_AHB_CLK>;

	status = "ok";

};

drivers/clk/qcom/Kconfig

+8 −0
Original line number Diff line number Diff line
@@ -423,3 +423,11 @@ config MSM_VIDEOCC_SDMMAGPIE 
	  SDMMAGPIE devices.

	  Say Y if you want to support video devices and functionality such as

	  video encode/decode.



config MSM_NPUCC_SDMMAGPIE

	tristate "SDMMAGPIE NPU Clock Controller"

	depends on COMMON_CLK_QCOM

	help

          Support for the NPU clock controller on Qualcomm Technologies, Inc

	  SDMMAGPIE devices.

	  Say Y if you want to enable use of the Network Processing Unit.

drivers/clk/qcom/Makefile

+1 −0
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@@ -55,6 +55,7 @@ obj-$(CONFIG_MSM_LCC_8960) += lcc-msm8960.o 
obj-$(CONFIG_MSM_MMCC_8960) += mmcc-msm8960.o

obj-$(CONFIG_MSM_MMCC_8974) += mmcc-msm8974.o

obj-$(CONFIG_MSM_MMCC_8996) += mmcc-msm8996.o

obj-$(CONFIG_MSM_NPUCC_SDMMAGPIE) += npucc-sdmmagpie.o

obj-$(CONFIG_MSM_NPUCC_SM8150) += npucc-sm8150.o

obj-$(CONFIG_MSM_VIDEOCC_SDMMAGPIE) += videocc-sdmmagpie.o

obj-$(CONFIG_MSM_VIDEOCC_SM6150) += videocc-sm6150.o