clk: mediatek: add clk support for MT6797

	---help---

	  This driver supports Mediatek MT2701 bdpsys clocks.

config COMMON_CLK_MT6797

       bool "Clock driver for Mediatek MT6797"

       depends on (ARCH_MEDIATEK && ARM64) || COMPILE_TEST

       select COMMON_CLK_MEDIATEK

       default ARCH_MEDIATEK && ARM64

       ---help---

         This driver supports Mediatek MT6797 basic clocks.

config COMMON_CLK_MT6797_MMSYS

       bool "Clock driver for Mediatek MT6797 mmsys"

       depends on COMMON_CLK_MT6797

       ---help---

         This driver supports Mediatek MT6797 mmsys clocks.

config COMMON_CLK_MT6797_IMGSYS

       bool "Clock driver for Mediatek MT6797 imgsys"

       depends on COMMON_CLK_MT6797

       ---help---

         This driver supports Mediatek MT6797 imgsys clocks.

config COMMON_CLK_MT6797_VDECSYS

       bool "Clock driver for Mediatek MT6797 vdecsys"

       depends on COMMON_CLK_MT6797

       ---help---

         This driver supports Mediatek MT6797 vdecsys clocks.

config COMMON_CLK_MT6797_VENCSYS

       bool "Clock driver for Mediatek MT6797 vencsys"

       depends on COMMON_CLK_MT6797

       ---help---

         This driver supports Mediatek MT6797 vencsys clocks.

config COMMON_CLK_MT8135

	bool "Clock driver for Mediatek MT8135"

	depends on (ARCH_MEDIATEK && ARM) || COMPILE_TEST

obj-$(CONFIG_COMMON_CLK_MEDIATEK) += clk-mtk.o clk-pll.o clk-gate.o clk-apmixed.o

obj-$(CONFIG_RESET_CONTROLLER) += reset.o

obj-$(CONFIG_COMMON_CLK_MT6797) += clk-mt6797.o

obj-$(CONFIG_COMMON_CLK_MT6797_IMGSYS) += clk-mt6797-img.o

obj-$(CONFIG_COMMON_CLK_MT6797_MMSYS) += clk-mt6797-mm.o

obj-$(CONFIG_COMMON_CLK_MT6797_VDECSYS) += clk-mt6797-vdec.o

obj-$(CONFIG_COMMON_CLK_MT6797_VENCSYS) += clk-mt6797-venc.o

obj-$(CONFIG_COMMON_CLK_MT2701) += clk-mt2701.o

obj-$(CONFIG_COMMON_CLK_MT2701_BDPSYS) += clk-mt2701-bdp.o

obj-$(CONFIG_COMMON_CLK_MT2701_ETHSYS) += clk-mt2701-eth.o

/* Copyright (c) 2017 MediaTek Inc.

 * Author: Kevin Chen <kevin-cw.chen@mediatek.com>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */

#include <linux/clk-provider.h>

#include <linux/platform_device.h>

#include <dt-bindings/clock/mt6797-clk.h>

#include "clk-mtk.h"

#include "clk-gate.h"

static const struct mtk_gate_regs img_cg_regs = {

	.set_ofs = 0x0004,

	.clr_ofs = 0x0008,

	.sta_ofs = 0x0000,

};

#define GATE_IMG(_id, _name, _parent, _shift) {		\

		.id = _id,				\

		.name = _name,				\

		.parent_name = _parent,			\

		.regs = &img_cg_regs,			\

		.shift = _shift,			\

		.ops = &mtk_clk_gate_ops_setclr,	\

	}

static const struct mtk_gate img_clks[] = {

	GATE_IMG(CLK_IMG_FDVT, "img_fdvt", "mm_sel", 11),

	GATE_IMG(CLK_IMG_DPE, "img_dpe", "mm_sel", 10),

	GATE_IMG(CLK_IMG_DIP, "img_dip", "mm_sel", 6),

	GATE_IMG(CLK_IMG_LARB6, "img_larb6", "mm_sel", 0),

};

static const struct of_device_id of_match_clk_mt6797_img[] = {

	{ .compatible = "mediatek,mt6797-imgsys", },

	{}

};

static int clk_mt6797_img_probe(struct platform_device *pdev)

{

	struct clk_onecell_data *clk_data;

	int r;

	struct device_node *node = pdev->dev.of_node;

	clk_data = mtk_alloc_clk_data(CLK_IMG_NR);

	mtk_clk_register_gates(node, img_clks, ARRAY_SIZE(img_clks),

			       clk_data);

	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);

	if (r)

		dev_err(&pdev->dev,

			"could not register clock provider: %s: %d\n",

			pdev->name, r);

	return r;

}

static struct platform_driver clk_mt6797_img_drv = {

	.probe = clk_mt6797_img_probe,

	.driver = {

		.name = "clk-mt6797-img",

		.of_match_table = of_match_clk_mt6797_img,

	},

};

builtin_platform_driver(clk_mt6797_img_drv);

/*

 * Copyright (c) 2017 MediaTek Inc.

 * Author: Kevin Chen <kevin-cw.chen@mediatek.com>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */

#include <linux/clk-provider.h>

#include <linux/platform_device.h>

#include <dt-bindings/clock/mt6797-clk.h>

#include "clk-mtk.h"

#include "clk-gate.h"

static const struct mtk_gate_regs mm0_cg_regs = {

	.set_ofs = 0x0104,

	.clr_ofs = 0x0108,

	.sta_ofs = 0x0100,

};

static const struct mtk_gate_regs mm1_cg_regs = {

	.set_ofs = 0x0114,

	.clr_ofs = 0x0118,

	.sta_ofs = 0x0110,

};

#define GATE_MM0(_id, _name, _parent, _shift) {			\

	.id = _id,					\

	.name = _name,					\

	.parent_name = _parent,				\

	.regs = &mm0_cg_regs,				\

	.shift = _shift,				\

	.ops = &mtk_clk_gate_ops_setclr,		\

}

#define GATE_MM1(_id, _name, _parent, _shift) {			\

	.id = _id,					\

	.name = _name,					\

	.parent_name = _parent,				\

	.regs = &mm1_cg_regs,				\

	.shift = _shift,				\

	.ops = &mtk_clk_gate_ops_setclr,		\

}

static const struct mtk_gate mm_clks[] = {

	GATE_MM0(CLK_MM_SMI_COMMON, "mm_smi_common", "mm_sel", 0),

	GATE_MM0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),

	GATE_MM0(CLK_MM_SMI_LARB5, "mm_smi_larb5", "mm_sel", 2),

	GATE_MM0(CLK_MM_CAM_MDP, "mm_cam_mdp", "mm_sel", 3),

	GATE_MM0(CLK_MM_MDP_RDMA0, "mm_mdp_rdma0", "mm_sel", 4),

	GATE_MM0(CLK_MM_MDP_RDMA1, "mm_mdp_rdma1", "mm_sel", 5),

	GATE_MM0(CLK_MM_MDP_RSZ0, "mm_mdp_rsz0", "mm_sel", 6),

	GATE_MM0(CLK_MM_MDP_RSZ1, "mm_mdp_rsz1", "mm_sel", 7),

	GATE_MM0(CLK_MM_MDP_RSZ2, "mm_mdp_rsz2", "mm_sel", 8),

	GATE_MM0(CLK_MM_MDP_TDSHP, "mm_mdp_tdshp", "mm_sel", 9),

	GATE_MM0(CLK_MM_MDP_COLOR, "mm_mdp_color", "mm_sel", 10),

	GATE_MM0(CLK_MM_MDP_WDMA, "mm_mdp_wdma", "mm_sel", 11),

	GATE_MM0(CLK_MM_MDP_WROT0, "mm_mdp_wrot0", "mm_sel", 12),

	GATE_MM0(CLK_MM_MDP_WROT1, "mm_mdp_wrot1", "mm_sel", 13),

	GATE_MM0(CLK_MM_FAKE_ENG, "mm_fake_eng", "mm_sel", 14),

	GATE_MM0(CLK_MM_DISP_OVL0, "mm_disp_ovl0", "mm_sel", 15),

	GATE_MM0(CLK_MM_DISP_OVL1, "mm_disp_ovl1", "mm_sel", 16),

	GATE_MM0(CLK_MM_DISP_OVL0_2L, "mm_disp_ovl0_2l", "mm_sel", 17),

	GATE_MM0(CLK_MM_DISP_OVL1_2L, "mm_disp_ovl1_2l", "mm_sel", 18),

	GATE_MM0(CLK_MM_DISP_RDMA0, "mm_disp_rdma0", "mm_sel", 19),

	GATE_MM0(CLK_MM_DISP_RDMA1, "mm_disp_rdma1", "mm_sel", 20),

	GATE_MM0(CLK_MM_DISP_WDMA0, "mm_disp_wdma0", "mm_sel", 21),

	GATE_MM0(CLK_MM_DISP_WDMA1, "mm_disp_wdma1", "mm_sel", 22),

	GATE_MM0(CLK_MM_DISP_COLOR, "mm_disp_color", "mm_sel", 23),

	GATE_MM0(CLK_MM_DISP_CCORR, "mm_disp_ccorr", "mm_sel", 24),

	GATE_MM0(CLK_MM_DISP_AAL, "mm_disp_aal", "mm_sel", 25),

	GATE_MM0(CLK_MM_DISP_GAMMA, "mm_disp_gamma", "mm_sel", 26),

	GATE_MM0(CLK_MM_DISP_OD, "mm_disp_od", "mm_sel", 27),

	GATE_MM0(CLK_MM_DISP_DITHER, "mm_disp_dither", "mm_sel", 28),

	GATE_MM0(CLK_MM_DISP_UFOE, "mm_disp_ufoe", "mm_sel", 29),

	GATE_MM0(CLK_MM_DISP_DSC, "mm_disp_dsc", "mm_sel", 30),

	GATE_MM0(CLK_MM_DISP_SPLIT, "mm_disp_split", "mm_sel", 31),

	GATE_MM1(CLK_MM_DSI0_MM_CLOCK, "mm_dsi0_mm_clock", "mm_sel", 0),

	GATE_MM1(CLK_MM_DSI1_MM_CLOCK, "mm_dsi1_mm_clock", "mm_sel", 2),

	GATE_MM1(CLK_MM_DPI_MM_CLOCK, "mm_dpi_mm_clock", "mm_sel", 4),

	GATE_MM1(CLK_MM_DPI_INTERFACE_CLOCK, "mm_dpi_interface_clock",

		 "dpi0_sel", 5),

	GATE_MM1(CLK_MM_LARB4_AXI_ASIF_MM_CLOCK, "mm_larb4_axi_asif_mm_clock",

		 "mm_sel", 6),

	GATE_MM1(CLK_MM_LARB4_AXI_ASIF_MJC_CLOCK, "mm_larb4_axi_asif_mjc_clock",

		 "mjc_sel", 7),

	GATE_MM1(CLK_MM_DISP_OVL0_MOUT_CLOCK, "mm_disp_ovl0_mout_clock",

		 "mm_sel", 8),

	GATE_MM1(CLK_MM_FAKE_ENG2, "mm_fake_eng2", "mm_sel", 9),

	GATE_MM1(CLK_MM_DSI0_INTERFACE_CLOCK, "mm_dsi0_interface_clock",

		 "clk26m", 1),

	GATE_MM1(CLK_MM_DSI1_INTERFACE_CLOCK, "mm_dsi1_interface_clock",

		 "clk26m", 3),

};

static const struct of_device_id of_match_clk_mt6797_mm[] = {

	{ .compatible = "mediatek,mt6797-mmsys", },

	{}

};

static int clk_mt6797_mm_probe(struct platform_device *pdev)

{

	struct clk_onecell_data *clk_data;

	int r;

	struct device_node *node = pdev->dev.of_node;

	clk_data = mtk_alloc_clk_data(CLK_MM_NR);

	mtk_clk_register_gates(node, mm_clks, ARRAY_SIZE(mm_clks),

			       clk_data);

	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);

	if (r)

		dev_err(&pdev->dev,

			"could not register clock provider: %s: %d\n",

			pdev->name, r);

	return r;

}

static struct platform_driver clk_mt6797_mm_drv = {

	.probe = clk_mt6797_mm_probe,

	.driver = {

		.name = "clk-mt6797-mm",

		.of_match_table = of_match_clk_mt6797_mm,

	},

};

builtin_platform_driver(clk_mt6797_mm_drv);

/*

 * Copyright (c) 2017 MediaTek Inc.

 * Author: Kevin-CW Chen <kevin-cw.chen@mediatek.com>

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 as

 * published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */

#include <linux/clk-provider.h>

#include <linux/platform_device.h>

#include "clk-mtk.h"

#include "clk-gate.h"

#include <dt-bindings/clock/mt6797-clk.h>

static const struct mtk_gate_regs vdec0_cg_regs = {

	.set_ofs = 0x0000,

	.clr_ofs = 0x0004,

	.sta_ofs = 0x0000,

};

static const struct mtk_gate_regs vdec1_cg_regs = {

	.set_ofs = 0x0008,

	.clr_ofs = 0x000c,

	.sta_ofs = 0x0008,

};

#define GATE_VDEC0(_id, _name, _parent, _shift) {		\

	.id = _id,					\

	.name = _name,					\

	.parent_name = _parent,				\

	.regs = &vdec0_cg_regs,				\

	.shift = _shift,				\

	.ops = &mtk_clk_gate_ops_setclr_inv,		\

}

#define GATE_VDEC1(_id, _name, _parent, _shift) {		\

	.id = _id,					\

	.name = _name,					\

	.parent_name = _parent,				\

	.regs = &vdec1_cg_regs,				\

	.shift = _shift,				\

	.ops = &mtk_clk_gate_ops_setclr_inv,		\

}

static const struct mtk_gate vdec_clks[] = {

	GATE_VDEC0(CLK_VDEC_CKEN_ENG, "vdec_cken_eng", "vdec_sel", 8),

	GATE_VDEC0(CLK_VDEC_ACTIVE, "vdec_active", "vdec_sel", 4),

	GATE_VDEC0(CLK_VDEC_CKEN, "vdec_cken", "vdec_sel", 0),

	GATE_VDEC1(CLK_VDEC_LARB1_CKEN, "vdec_larb1_cken", "mm_sel", 0),

};

static const struct of_device_id of_match_clk_mt6797_vdec[] = {

	{ .compatible = "mediatek,mt6797-vdecsys", },

	{}

};

static int clk_mt6797_vdec_probe(struct platform_device *pdev)

{

	struct clk_onecell_data *clk_data;

	int r;

	struct device_node *node = pdev->dev.of_node;

	clk_data = mtk_alloc_clk_data(CLK_VDEC_NR);

	mtk_clk_register_gates(node, vdec_clks, ARRAY_SIZE(vdec_clks),

			       clk_data);

	r = of_clk_add_provider(node, of_clk_src_onecell_get, clk_data);

	if (r)

		dev_err(&pdev->dev,

			"could not register clock provider: %s: %d\n",

			pdev->name, r);

	return r;

}

static struct platform_driver clk_mt6797_vdec_drv = {

	.probe = clk_mt6797_vdec_probe,

	.driver = {

		.name = "clk-mt6797-vdec",

		.of_match_table = of_match_clk_mt6797_vdec,

	},

};

builtin_platform_driver(clk_mt6797_vdec_drv);