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Commit 94cdda6b authored by Arnaldo Carvalho de Melo's avatar Arnaldo Carvalho de Melo
Browse files

perf tools: Move sparc barrier.h stuff to tools/arch/sparc/include/asm/barrier.h 

We will need it for atomic.h, so move it from the ad-hoc tools/perf/
place to a tools/ subset of the kernel arch/ hierarchy.

Cc: Adrian Hunter <adrian.hunter@intel.com>
Cc: Borislav Petkov <bp@suse.de>
Cc: David Ahern <dsahern@gmail.com>
Cc: Don Zickus <dzickus@redhat.com>
Cc: Frederic Weisbecker <fweisbec@gmail.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Stephane Eranian <eranian@google.com>
Link: http://lkml.kernel.org/n/tip-f0d04b9x63grt30nahpw9ei0@git.kernel.org


Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 827634ad

tools/arch/sparc/include/asm/barrier.h

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#ifndef ___TOOLS_LINUX_ASM_SPARC_BARRIER_H

#define ___TOOLS_LINUX_ASM_SPARC_BARRIER_H

#if defined(__sparc__) && defined(__arch64__)

#include "barrier_64.h"

#else

#include "barrier_32.h"

#endif

#endif

tools/arch/sparc/include/asm/barrier_32.h

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#ifndef __TOOLS_PERF_SPARC_BARRIER_H

#define __TOOLS_PERF_SPARC_BARRIER_H



#include <asm-generic/barrier.h>



#endif /* !(__TOOLS_PERF_SPARC_BARRIER_H) */

tools/arch/sparc/include/asm/barrier_64.h

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#ifndef __TOOLS_LINUX_SPARC64_BARRIER_H

#define __TOOLS_LINUX_SPARC64_BARRIER_H



/* Copied from the kernel sources to tools/:

 *

 * These are here in an effort to more fully work around Spitfire Errata

 * #51.  Essentially, if a memory barrier occurs soon after a mispredicted

 * branch, the chip can stop executing instructions until a trap occurs.

 * Therefore, if interrupts are disabled, the chip can hang forever.

 *

 * It used to be believed that the memory barrier had to be right in the

 * delay slot, but a case has been traced recently wherein the memory barrier

 * was one instruction after the branch delay slot and the chip still hung.

 * The offending sequence was the following in sym_wakeup_done() of the

 * sym53c8xx_2 driver:

 *

 *	call	sym_ccb_from_dsa, 0

 *	 movge	%icc, 0, %l0

 *	brz,pn	%o0, .LL1303

 *	 mov	%o0, %l2

 *	membar	#LoadLoad

 *

 * The branch has to be mispredicted for the bug to occur.  Therefore, we put

 * the memory barrier explicitly into a "branch always, predicted taken"

 * delay slot to avoid the problem case.

 */

#define membar_safe(type) \

do {	__asm__ __volatile__("ba,pt	%%xcc, 1f\n\t" \

			     " membar	" type "\n" \

			     "1:\n" \

			     : : : "memory"); \

} while (0)



/* The kernel always executes in TSO memory model these days,

 * and furthermore most sparc64 chips implement more stringent

 * memory ordering than required by the specifications.

 */

#define mb()	membar_safe("#StoreLoad")

#define rmb()	__asm__ __volatile__("":::"memory")

#define wmb()	__asm__ __volatile__("":::"memory")



#endif /* !(__TOOLS_LINUX_SPARC64_BARRIER_H) */

tools/include/asm/barrier.h

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@@ -6,4 +6,6 @@ 
#include "../../arch/s390/include/asm/barrier.h"

#elif defined(__sh__)

#include "../../arch/sh/include/asm/barrier.h"

#elif defined(__sparc__)

#include "../../arch/sparc/include/asm/barrier.h"

#endif

tools/perf/MANIFEST

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@@ -2,6 +2,9 @@ tools/perf 
tools/arch/powerpc/include/asm/barrier.h

tools/arch/s390/include/asm/barrier.h

tools/arch/sh/include/asm/barrier.h

tools/arch/sparc/include/asm/barrier.h

tools/arch/sparc/include/asm/barrier_32.h

tools/arch/sparc/include/asm/barrier_64.h

tools/arch/x86/include/asm/barrier.h

tools/scripts

tools/build