Donate to e Foundation | Murena handsets with /e/OS | Own a part of Murena! Learn more

Commit 907d442b authored by Xiaowen Wu's avatar Xiaowen Wu
Browse files

drm/msm: ignore HS TX timeout when bllp_lp11 is disabled



When bllp_lp11 is disabled, HW is configured to stay in HS in the entire
frame and always trigger HS TX timeout. This change will disable the
interrupt and error handling for this special configuration.

Change-Id: I0e5fdf28c7d878c5d431d56e7928bb0b947a75e7
Signed-off-by: default avatarXiaowen Wu <wxiaowen@codeaurora.org>
parent 3638c290
Loading
Loading
Loading
Loading
+23 −2
Original line number Original line Diff line number Diff line
@@ -1588,6 +1588,18 @@ static int dsi_disable_ulps(struct dsi_ctrl *dsi_ctrl)
	return rc;
	return rc;
}
}


static void dsi_ctrl_enable_error_interrupts(struct dsi_ctrl *dsi_ctrl)
{
	if (dsi_ctrl->host_config.panel_mode == DSI_OP_VIDEO_MODE &&
			!dsi_ctrl->host_config.u.video_engine.bllp_lp11_en &&
			!dsi_ctrl->host_config.u.video_engine.eof_bllp_lp11_en)
		dsi_ctrl->hw.ops.enable_error_interrupts(&dsi_ctrl->hw,
				0xFF00A0);
	else
		dsi_ctrl->hw.ops.enable_error_interrupts(&dsi_ctrl->hw,
				0xFF00E0);
}

static int dsi_ctrl_drv_state_init(struct dsi_ctrl *dsi_ctrl)
static int dsi_ctrl_drv_state_init(struct dsi_ctrl *dsi_ctrl)
{
{
	int rc = 0;
	int rc = 0;
@@ -2198,7 +2210,9 @@ int dsi_ctrl_setup(struct dsi_ctrl *dsi_ctrl)
	}
	}


	dsi_ctrl->hw.ops.enable_status_interrupts(&dsi_ctrl->hw, 0x0);
	dsi_ctrl->hw.ops.enable_status_interrupts(&dsi_ctrl->hw, 0x0);
	dsi_ctrl->hw.ops.enable_error_interrupts(&dsi_ctrl->hw, 0xFF00E0);

	dsi_ctrl_enable_error_interrupts(dsi_ctrl);

	dsi_ctrl->hw.ops.ctrl_en(&dsi_ctrl->hw, true);
	dsi_ctrl->hw.ops.ctrl_en(&dsi_ctrl->hw, true);


	mutex_unlock(&dsi_ctrl->ctrl_lock);
	mutex_unlock(&dsi_ctrl->ctrl_lock);
@@ -2321,6 +2335,12 @@ static void dsi_ctrl_handle_error_status(struct dsi_ctrl *dsi_ctrl,
	if (error & 0x3000E00)
	if (error & 0x3000E00)
		pr_err("dsi PHY contention error: 0x%lx\n", error);
		pr_err("dsi PHY contention error: 0x%lx\n", error);


	/* ignore TX timeout if blpp_lp11 is disabled */
	if (dsi_ctrl->host_config.panel_mode == DSI_OP_VIDEO_MODE &&
			!dsi_ctrl->host_config.u.video_engine.bllp_lp11_en &&
			!dsi_ctrl->host_config.u.video_engine.eof_bllp_lp11_en)
		error &= ~DSI_HS_TX_TIMEOUT;

	/* TX timeout error */
	/* TX timeout error */
	if (error & 0xE0) {
	if (error & 0xE0) {
		if (error & 0xA0) {
		if (error & 0xA0) {
@@ -2701,7 +2721,8 @@ int dsi_ctrl_host_init(struct dsi_ctrl *dsi_ctrl, bool is_splash_enabled)
	}
	}


	dsi_ctrl->hw.ops.enable_status_interrupts(&dsi_ctrl->hw, 0x0);
	dsi_ctrl->hw.ops.enable_status_interrupts(&dsi_ctrl->hw, 0x0);
	dsi_ctrl->hw.ops.enable_error_interrupts(&dsi_ctrl->hw, 0xFF00E0);

	dsi_ctrl_enable_error_interrupts(dsi_ctrl);


	pr_debug("[DSI_%d]Host initialization complete, continuous splash status:%d\n",
	pr_debug("[DSI_%d]Host initialization complete, continuous splash status:%d\n",
		dsi_ctrl->cell_index, is_splash_enabled);
		dsi_ctrl->cell_index, is_splash_enabled);