Merge "ARM: dts: msm: Specify L3 GPU voter power levels on sm8150" (8fee9271) · Commits · e / devices / android_kernel_oneplus_sm8150

Documentation/devicetree/bindings/gpu/adreno.txt

+16 −2

Original line number	Diff line number	Diff line
		@@ -29,7 +29,7 @@ Required properties:
		Current values of clock-names are:
		"src_clk", "core_clk", "iface_clk", "mem_clk", "mem_iface_clk",
		"alt_mem_iface_clk", "rbbmtimer_clk", "alwayson_clk",
		"iref_clk"
		"iref_clk", "l3_vote"
		"core_clk" and "iface_clk" are required and others are optional

		- qcom,base-leakage-coefficient: Dynamic leakage coefficient.
		@@ -78,7 +78,6 @@ IOMMU Data:
		GPU Power levels:
		- qcom,gpu-pwrlevel-bins: Container for sets of GPU power levels (see
		adreno-pwrlevels.txt)

		DCVS Core info
		- qcom,dcvs-core-info Container for the DCVS core info (see
		dcvs-core-info.txt)
		@@ -262,6 +261,21 @@ GPU LLC slice info:
		and pagetable walk.
		- cache-slices: phandle to the system LLC driver, cache slice index.

		L3 Power levels:
		- qcom,l3-pwrlevels: Container for sets of L3 power levels, the
		L3 frequency is adjusted according to the
		performance hint received from userspace.

		Properties:
		- compatible: Must be qcom,l3-pwrlevels
		- qcom,l3-pwrlevel: A single L3 powerlevel

		Properties:
		- reg: Index of the L3 powerlevel
		0 = powerlevel for no L3 vote
		1 = powerlevel for medium L3 vote
		2 = powerlevel for maximum L3 vote
		- qcom,l3-freq: The L3 frequency for the powerlevel (in Hz)

		GPU coresight info:
		The following properties are optional as collecting data via coresight might

arch/arm64/boot/dts/qcom/sm8150-gpu.dtsi

+25 −2

Original line number	Diff line number	Diff line
		@@ -99,11 +99,12 @@
		<&clock_gcc GCC_DDRSS_GPU_AXI_CLK>,
		<&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>,
		<&clock_gpucc GPU_CC_CX_GMU_CLK>,
		<&clock_gpucc GPU_CC_AHB_CLK>;
		<&clock_gpucc GPU_CC_AHB_CLK>,
		<&clock_cpucc L3_GPU_VOTE_CLK>;

		clock-names = "rbbmtimer_clk", "mem_clk",
		"mem_iface_clk", "gmu_clk",
		"gpu_cc_ahb";
		"gpu_cc_ahb", "l3_vote";

		qcom,isense-clk-on-level = <1>;

		@@ -143,6 +144,28 @@
		cache-slice-names = "gpu", "gpuhtw";
		cache-slices = <&llcc 12>, <&llcc 11>;

		qcom,l3-pwrlevels {
		#address-cells = <1>;
		#size-cells = <0>;

		compatible = "qcom,l3-pwrlevels";

		qcom,l3-pwrlevel@0 {
		reg = <0>;
		qcom,l3-freq = <0>;
		};

		qcom,l3-pwrlevel@1 {
		reg = <1>;
		qcom,l3-freq = <864000000>;
		};

		qcom,l3-pwrlevel@2 {
		reg = <2>;
		qcom,l3-freq = <1344000000>;
		};
		};

		/* GPU Mempools */
		qcom,gpu-mempools {
		#address-cells = <1>;

arch/arm64/boot/dts/qcom/sm8150.dtsi

+2 −1

Original line number	Diff line number	Diff line
		@@ -1471,7 +1471,8 @@
		<0x18327800 0x1400>;
		reg-names = "osm_l3_base", "osm_pwrcl_base",
		"osm_perfcl_base", "osm_perfpcl_base";
		l3-devs = <&cpu0_cpu_l3_lat &cpu4_cpu_l3_lat &cdsp_cdsp_l3_lat>;
		l3-devs = <&cpu0_cpu_l3_lat &cpu4_cpu_l3_lat &cdsp_cdsp_l3_lat
		&msm_gpu>;

		#clock-cells = <1>;
		};

drivers/gpu/msm/adreno.c

+70 −1

Original line number	Diff line number	Diff line
		@@ -1037,6 +1037,41 @@ static int adreno_of_get_pwrlevels(struct adreno_device *adreno_dev,
		return -ENODEV;
		}

		static void
		l3_pwrlevel_probe(struct kgsl_device device, struct device_node node)
		{
		struct device_node pwrlevel_node, child;

		pwrlevel_node = of_find_node_by_name(node, "qcom,l3-pwrlevels");

		if (pwrlevel_node == NULL)
		return;

		for_each_available_child_of_node(pwrlevel_node, child) {
		unsigned int index;

		if (of_property_read_u32(child, "reg", &index))
		return;
		if (index >= MAX_L3_LEVELS)
		continue;

		if (index >= device->num_l3_pwrlevels)
		device->num_l3_pwrlevels = index + 1;

		if (of_property_read_u32(child, "qcom,l3-freq",
		&device->l3_freq[index]))
		continue;
		}

		device->l3_clk = devm_clk_get(&device->pdev->dev, "l3_vote");

		if (IS_ERR_OR_NULL(device->l3_clk)) {
		dev_err(&device->pdev->dev,
		"Unable to get the l3_vote clock\n");
		device->l3_clk = NULL;
		}
		}

		static inline struct adreno_device adreno_get_dev(struct platform_device pdev)
		{
		const struct of_device_id *of_id =
		@@ -1083,6 +1118,8 @@ static int adreno_of_get_power(struct adreno_device *adreno_dev,
		/* Get context aware DCVS properties */
		adreno_of_get_ca_aware_properties(adreno_dev, node);

		l3_pwrlevel_probe(device, node);

		/* get pm-qos-active-latency, set it to default if not found */
		if (of_property_read_u32(node, "qcom,pm-qos-active-latency",
		&device->pwrctrl.pm_qos_active_latency))
		@@ -2619,7 +2656,38 @@ int adreno_set_constraint(struct kgsl_device *device,
		context->pwr_constraint.sub_type);
		context->pwr_constraint.type = KGSL_CONSTRAINT_NONE;
		break;
		case KGSL_CONSTRAINT_L3_PWRLEVEL: {
		struct kgsl_device_constraint_pwrlevel pwr;

		if (constraint->size != sizeof(pwr)) {
		status = -EINVAL;
		break;
		}

		if (copy_from_user(&pwr, constraint->data, sizeof(pwr))) {
		status = -EFAULT;
		break;
		}
		if (pwr.level >= KGSL_CONSTRAINT_PWR_MAXLEVELS)
		pwr.level = KGSL_CONSTRAINT_PWR_MAXLEVELS - 1;

		context->l3_pwr_constraint.type = KGSL_CONSTRAINT_L3_PWRLEVEL;
		context->l3_pwr_constraint.sub_type = pwr.level;
		trace_kgsl_user_pwrlevel_constraint(device, context->id,
		context->l3_pwr_constraint.type,
		context->l3_pwr_constraint.sub_type);
		}
		break;
		case KGSL_CONSTRAINT_L3_NONE: {
		unsigned int type = context->l3_pwr_constraint.type;

		if (type == KGSL_CONSTRAINT_L3_PWRLEVEL)
		trace_kgsl_user_pwrlevel_constraint(device, context->id,
		KGSL_CONSTRAINT_L3_NONE,
		context->l3_pwr_constraint.sub_type);
		context->l3_pwr_constraint.type = KGSL_CONSTRAINT_L3_NONE;
		}
		break;
		default:
		status = -EINVAL;
		break;
		@@ -2680,7 +2748,8 @@ static int adreno_setproperty(struct kgsl_device_private *dev_priv,
		status = 0;
		}
		break;
		case KGSL_PROP_PWR_CONSTRAINT: {
		case KGSL_PROP_PWR_CONSTRAINT:
		case KGSL_PROP_L3_PWR_CONSTRAINT: {
		struct kgsl_device_constraint constraint;
		struct kgsl_context *context;

drivers/gpu/msm/adreno_compat.c

+3 −2

Original line number	Diff line number	Diff line
		/* Copyright (c) 2013-2017, The Linux Foundation. All rights reserved.
		/* Copyright (c) 2013-2018, The Linux Foundation. All rights reserved.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 and
		@@ -158,7 +158,8 @@ int adreno_setproperty_compat(struct kgsl_device_private *dev_priv,
		struct kgsl_device *device = dev_priv->device;

		switch (type) {
		case KGSL_PROP_PWR_CONSTRAINT: {
		case KGSL_PROP_PWR_CONSTRAINT:
		case KGSL_PROP_L3_PWR_CONSTRAINT: {
		struct kgsl_device_constraint_compat constraint32;
		struct kgsl_device_constraint constraint;
		struct kgsl_context *context;