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Commit f8fb6e05 authored by Lynus Vaz's avatar Lynus Vaz
Browse files

ARM: dts: msm: Specify L3 GPU voter power levels on sm8150 



Specify the L3 power levels the GPU driver can vote for on sm8150.

Change-Id: I4bde25d59c873b6b7af2c08b2445b44bdeeaa797
Signed-off-by: default avatarLynus Vaz <lvaz@codeaurora.org>
parent c087b71f

arch/arm64/boot/dts/qcom/sm8150-gpu.dtsi

+25 −2
Original line number Diff line number Diff line
@@ -99,11 +99,12 @@ 
			<&clock_gcc GCC_DDRSS_GPU_AXI_CLK>,

			<&clock_gcc GCC_GPU_MEMNOC_GFX_CLK>,

			<&clock_gpucc GPU_CC_CX_GMU_CLK>,

			<&clock_gpucc GPU_CC_AHB_CLK>;

			<&clock_gpucc GPU_CC_AHB_CLK>,

			<&clock_cpucc L3_GPU_VOTE_CLK>;



		clock-names = "rbbmtimer_clk", "mem_clk",

				"mem_iface_clk", "gmu_clk",

				"gpu_cc_ahb";

				"gpu_cc_ahb", "l3_vote";



		qcom,isense-clk-on-level = <1>;
@@ -143,6 +144,28 @@ 
		cache-slice-names = "gpu", "gpuhtw";

		cache-slices = <&llcc 12>, <&llcc 11>;



		qcom,l3-pwrlevels {

			#address-cells = <1>;

			#size-cells = <0>;



			compatible = "qcom,l3-pwrlevels";



			qcom,l3-pwrlevel@0 {

				reg = <0>;

				qcom,l3-freq = <0>;

			};



			qcom,l3-pwrlevel@1 {

				reg = <1>;

				qcom,l3-freq = <864000000>;

			};



			qcom,l3-pwrlevel@2 {

				reg = <2>;

				qcom,l3-freq = <1344000000>;

			};

		};



		/* GPU Mempools */

		qcom,gpu-mempools {

			#address-cells = <1>;

arch/arm64/boot/dts/qcom/sm8150.dtsi

+2 −1
Original line number Diff line number Diff line
@@ -1471,7 +1471,8 @@ 
			<0x18327800 0x1400>;

		reg-names = "osm_l3_base", "osm_pwrcl_base",

			"osm_perfcl_base", "osm_perfpcl_base";

		l3-devs = <&cpu0_cpu_l3_lat &cpu4_cpu_l3_lat &cdsp_cdsp_l3_lat>;

		l3-devs = <&cpu0_cpu_l3_lat &cpu4_cpu_l3_lat &cdsp_cdsp_l3_lat

			&msm_gpu>;



		#clock-cells = <1>;

	};