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Commit 8fe0116e authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add GPU coresight properties for SM8150"

parents 8ec4e39d c6efa3f2

Documentation/devicetree/bindings/gpu/adreno.txt

+5 −2
Original line number Diff line number Diff line
@@ -8,7 +8,8 @@ Required properties: 
- reg:			Specifies the register base address and size, the shader memory

			base address and size (if it exists), base address and size

			of the CX_DBGC block (if it exists), and the base address and

			size of the CX_MISC block (if it exists).

			size of the CX_MISC block (if it exists), and the base address and size of

			QDSS_GFX block (if it exists).

- reg-names:		Resource names used for the physical address of device registers

			and shader memory. "kgsl_3d0_reg_memory" gives the physical address

			and length of device registers while "kgsl_3d0_shader_memory" gives
@@ -17,7 +18,9 @@ Required properties: 
			registers used for various configuration options. If specified,

			"kgsl_3d0_cx_dbgc_memory" gives the physical address and length

			of the CX DBGC block. If specified, "cx_misc" gives

			the physical address and length of the CX_MISC block.

			the physical address and length of the CX_MISC block. If specified,

			"qdss_gfx" provides the physical address and length of the

			QDSS_GFX_DBG block.

- interrupts:		Interrupt mapping for GPU IRQ.

- interrupt-names:	String property to describe the name of the interrupt.

- qcom,id:		An integer used as an identification number for the device.

arch/arm64/boot/dts/qcom/sm8150-coresight.dtsi

+52 −5
Original line number Diff line number Diff line
@@ -635,7 +635,6 @@ 
		ports {

			#address-cells = <1>;

			#size-cells = <0>;



			port@0 {

				reg = <0>;

				funnel_in2_out_funnel_merg: endpoint {
@@ -643,18 +642,24 @@ 
					  <&funnel_merg_in_funnel_in2>;

				};

			};



			port@1 {

				reg = <2>;

				reg = <1>;

				funnel_in2_in_funnel_apss_merg: endpoint {

					slave-mode;

					remote-endpoint =

					  <&funnel_apss_merg_out_funnel_in2>;

				};



			};

			port@2 {

				reg = <4>;

				reg = <2>;

				funnel_in2_in_funnel_gfx: endpoint {

					slave-mode;

					remote-endpoint =

					  <&funnel_gfx_out_funnel_in2>;

				};

			};

			port@3 {

				reg = <3>;

				funnel_in2_in_tpda_modem: endpoint {

					slave-mode;

					remote-endpoint =
@@ -664,6 +669,48 @@ 
		};

	};



	funnel_gfx: funnel@0x6943000 {

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b908>;



		reg = <0x6943000 0x1000>;

		reg-names = "funnel-base";



		coresight-name = "coresight-funnel-gfx";



		clocks = <&clock_aop QDSS_CLK>;

		clock-names = "apb_pclk";



		ports {

			#address-cells = <1>;

			#size-cells = <0>;



			port@0 {

				reg = <0>;

				funnel_gfx_out_funnel_in2: endpoint {

					remote-endpoint =

					  <&funnel_in2_in_funnel_gfx>;

				};

			};

			port@1 {

				reg = <1>;

				funnel_gfx_in_gfx: endpoint {

					slave-mode;

					remote-endpoint =

					  <&gfx_out_funnel_gfx>;

				};

			};

			port@2 {

				reg = <2>;

				funnel_gfx_in_gfx_cx: endpoint {

					slave-mode;

					remote-endpoint =

					  <&gfx_cx_out_funnel_gfx>;

				};

			};

		};

	};



	tpda: tpda@6004000 {

		compatible = "arm,primecell";

		arm,primecell-periphid = <0x0003b969>;

arch/arm64/boot/dts/qcom/sm8150-gpu.dtsi

+33 −2
Original line number Diff line number Diff line
@@ -67,8 +67,9 @@ 
		label = "kgsl-3d0";

		compatible = "qcom,kgsl-3d0", "qcom,kgsl-3d";

		status = "ok";

		reg = <0x2c00000 0x40000>, <0x2c61000 0x800>;

		reg-names = "kgsl_3d0_reg_memory", "cx_dbgc";

		reg = <0x2c00000 0x40000>, <0x2c61000 0x800>,

				<0x6900000 0x44000>;

		reg-names = "kgsl_3d0_reg_memory", "cx_dbgc", "qdss_gfx";

		interrupts = <0 300 0>;

		interrupt-names = "kgsl_3d0_irq";

		qcom,id = <0>;
@@ -147,6 +148,36 @@ 
		cache-slice-names = "gpu", "gpuhtw";

		cache-slices = <&llcc 12>, <&llcc 11>;





		qcom,gpu-coresights {

			#address-cells = <1>;

			#size-cells = <0>;

			compatible = "qcom,gpu-coresight";



			qcom,gpu-coresight@0 {

				reg = <0>;

				coresight-name = "coresight-gfx";

				coresight-atid = <50>;

				port {

					gfx_out_funnel_gfx: endpoint {

						remote-endpoint =

						  <&funnel_gfx_in_gfx>;

					};

				};

			};

			qcom,gpu-coresight@1 {

				reg = <1>;

				coresight-name = "coresight-gfx-cx";

				coresight-atid = <51>;

				port {

					gfx_cx_out_funnel_gfx: endpoint {

						remote-endpoint =

						  <&funnel_gfx_in_gfx_cx>;

					};

				};

			};

		};



		qcom,l3-pwrlevels {

			#address-cells = <1>;

			#size-cells = <0>;

drivers/gpu/msm/a6xx_reg.h

+24 −0
Original line number Diff line number Diff line
@@ -532,6 +532,30 @@ 
#define A6XX_RBBM_CLOCK_DELAY_HLSQ       0x0011c

#define A6XX_RBBM_CLOCK_HYST_HLSQ        0x0011d



/* ISDB SP0 and SP1 registers */

#define A6XX_SP0_ISDB_ISDB_EN                           0xf40001

#define A6XX_SP0_ISDB_ISDB_BRKPT_CFG                    0xf40005

#define A6XX_SP0_ISDB_ISDB_SHADER_ID_CFG                0xf40006

#define A6XX_SP0_ISDB_ISDB_WAVE_ID_CFG                  0xf40007

#define A6XX_SP0_ISDB_ISDB_SAC_CFG                      0xf40024

#define A6XX_SP0_ISDB_ISDB_SAC_ADDR_0                   0xf40020

#define A6XX_SP0_ISDB_ISDB_SAC_ADDR_1                   0xf40021

#define A6XX_SP0_ISDB_ISDB_SAC_MASK_0                   0xf40022

#define A6XX_SP0_ISDB_ISDB_SAC_MASK_1                   0xf40023

#define A6XX_HLSQ_ISDB_ISDB_HLSQ_ISDB_CL_WGID_CTRL      0xf44000

#define A6XX_HLSQ_ISDB_ISDB_HLSQ_ISDB_CL_WGID_X         0xf44001

#define A6XX_HLSQ_ISDB_ISDB_HLSQ_ISDB_CL_WGID_Y         0xf44002

#define A6XX_HLSQ_ISDB_ISDB_HLSQ_ISDB_CL_WGID_Z         0xf44003

#define A6XX_SP1_ISDB_ISDB_EN                           0xf40401

#define A6XX_SP1_ISDB_ISDB_SAC_CFG                      0xf40424

#define A6XX_SP1_ISDB_ISDB_SAC_ADDR_0                   0xf40420

#define A6XX_SP1_ISDB_ISDB_SAC_ADDR_1                   0xf40421

#define A6XX_SP1_ISDB_ISDB_SAC_MASK_0                   0xf40422

#define A6XX_SP1_ISDB_ISDB_SAC_MASK_1                   0xf40423

#define A6XX_SP1_ISDB_ISDB_SHADER_ID_CFG                0xf40406

#define A6XX_SP1_ISDB_ISDB_WAVE_ID_CFG                  0xf40407

#define A6XX_SP1_ISDB_ISDB_BRKPT_CFG                    0xf40405



/* DBGC_CFG registers */

#define A6XX_DBGC_CFG_DBGBUS_SEL_A                  0x600

#define A6XX_DBGC_CFG_DBGBUS_SEL_B                  0x601

drivers/gpu/msm/adreno.c

+23 −0
Original line number Diff line number Diff line
@@ -1241,6 +1241,26 @@ static void adreno_cx_misc_probe(struct kgsl_device *device) 
					res->start, adreno_dev->cx_misc_len);

}



static void adreno_qdss_dbg_probe(struct kgsl_device *device)

{

	struct adreno_device *adreno_dev = ADRENO_DEVICE(device);

	struct resource *res;



	res = platform_get_resource_byname(device->pdev, IORESOURCE_MEM,

					   "qdss_gfx");



	if (res == NULL)

		return;



	adreno_dev->qdss_gfx_base = res->start - device->reg_phys;

	adreno_dev->qdss_gfx_len = resource_size(res);

	adreno_dev->qdss_gfx_virt = devm_ioremap(device->dev, res->start,

						resource_size(res));



	if (adreno_dev->qdss_gfx_virt == NULL)

		KGSL_DRV_WARN(device, "qdss_gfx ioremap failed\n");

}



static void adreno_efuse_read_soc_hw_rev(struct adreno_device *adreno_dev)

{

	unsigned int val;
@@ -1376,6 +1396,9 @@ static int adreno_probe(struct platform_device *pdev) 
	/* Probe for the optional CX_MISC block */

	adreno_cx_misc_probe(device);



	/*Probe for the optional QDSS_GFX_DBG block*/

	adreno_qdss_dbg_probe(device);



	/*

	 * qcom,iommu-secure-id is used to identify MMUs that can handle secure

	 * content but that is only part of the story - the GPU also has to be