Merge "msm: pcie: add support for varying PCIe PHY status bit" (8f765160) · Commits · e / devices / android_kernel_oneplus_sm8150

Documentation/devicetree/bindings/pci/msm_pcie.txt

+2 −0

Original line number	Diff line number	Diff line
		@@ -30,6 +30,7 @@ Required properties:
		- perst-gpio: PERST GPIO specified by PCIe spec.
		- wake-gpio: WAKE GPIO specified by PCIe spec.
		- phy-status-offset: Offset from PCIe PHY base to check if PCIe PHY is up.
		- phy-status-bit: BIT to check PCIe PHY status.
		- pcie_rc<PCIe index>: PCI node is a sub-node of PCIe controller node.
		node. This node holds root complex specific configurations and properties.
		- <supply-name>-supply: phandle to the regulator device tree node.
		@@ -281,6 +282,7 @@ Example:
		qcom,wr-halt-size = <0xa>; /* 1KB */
		qcom,slv-addr-space-size = <0x1000000>; /* 16MB */
		qcom,phy-status-offset = <0x800>;
		qcom,phy-status-status = <6>;
		qcom,phy-power-down-offset = <0x840>;
		qcom,cpl-timeout = <0x2>;

arch/arm64/boot/dts/qcom/sa6155-pcie.dtsi

+2 −1

Original line number	Diff line number	Diff line
		/*
		* Copyright (c) 2018, The Linux Foundation. All rights reserved.
		* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 and
		@@ -189,6 +189,7 @@
		qcom,slv-addr-space-size = <0x20000000>;

		qcom,phy-status-offset = <0x974>;
		qcom,phy-status-bit = <6>;
		qcom,phy-power-down-offset = <0x804>;

		qcom,boot-option = <0x1>;

arch/arm64/boot/dts/qcom/sm8150-pcie.dtsi

+3 −1

Original line number	Diff line number	Diff line
		/*
		* Copyright (c) 2018, The Linux Foundation. All rights reserved.
		* Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 and
		@@ -173,6 +173,7 @@
		qcom,slv-addr-space-size = <0x4000000>;

		qcom,phy-status-offset = <0x814>;
		qcom,phy-status-bit = <6>;
		qcom,phy-power-down-offset = <0x840>;

		qcom,boot-option = <0x1>;
		@@ -489,6 +490,7 @@
		qcom,slv-addr-space-size = <0x20000000>;

		qcom,phy-status-offset = <0xa14>;
		qcom,phy-status-bit = <6>;
		qcom,phy-power-down-offset = <0xa40>;

		qcom,boot-option = <0x1>;

drivers/pci/host/pci-msm.c

+20 −2

Original line number	Diff line number	Diff line
		/* Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.
		/* Copyright (c) 2014-2019, The Linux Foundation. All rights reserved.
		*
		* This program is free software; you can redistribute it and/or modify
		* it under the terms of the GNU General Public License version 2 and
		@@ -590,6 +590,7 @@ struct msm_pcie_dev_t {
		uint32_t wr_halt_size;
		uint32_t slv_addr_space_size;
		uint32_t phy_status_offset;
		uint32_t phy_status_bit;
		uint32_t phy_power_down_offset;
		uint32_t cpl_timeout;
		uint32_t current_bdf;
		@@ -1001,7 +1002,8 @@ static void pcie_phy_init(struct msm_pcie_dev_t *dev)

		static bool pcie_phy_is_ready(struct msm_pcie_dev_t *dev)
		{
		if (readl_relaxed(dev->phy + dev->phy_status_offset) & BIT(6))
		if (readl_relaxed(dev->phy + dev->phy_status_offset) &
		BIT(dev->phy_status_bit))
		return false;
		else
		return true;
		@@ -1241,6 +1243,8 @@ static void msm_pcie_show_status(struct msm_pcie_dev_t *dev)
		dev->slv_addr_space_size);
		PCIE_DBG_FS(dev, "phy_status_offset: 0x%x\n",
		dev->phy_status_offset);
		PCIE_DBG_FS(dev, "phy_status_bit: %u\n",
		dev->phy_status_bit);
		PCIE_DBG_FS(dev, "phy_power_down_offset: 0x%x\n",
		dev->phy_power_down_offset);
		PCIE_DBG_FS(dev, "cpl_timeout: 0x%x\n",
		@@ -5563,6 +5567,20 @@ static int msm_pcie_probe(struct platform_device *pdev)
		rc_idx, msm_pcie_dev[rc_idx].phy_status_offset);
		}

		ret = of_property_read_u32(pdev->dev.of_node,
		"qcom,phy-status-bit",
		&msm_pcie_dev[rc_idx].phy_status_bit);
		if (ret) {
		PCIE_ERR(&msm_pcie_dev[rc_idx],
		"RC%d: failed to get PCIe PHY status bit.\n",
		rc_idx);
		goto decrease_rc_num;
		} else {
		PCIE_DBG(&msm_pcie_dev[rc_idx],
		"RC%d: phy-status-bit: 0x%x.\n",
		rc_idx, msm_pcie_dev[rc_idx].phy_status_bit);
		}

		msm_pcie_dev[rc_idx].phy_power_down_offset = 0;
		ret = of_property_read_u32(pdev->dev.of_node,
		"qcom,phy-power-down-offset",