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Commit 51d0318d authored by Tony Truong's avatar Tony Truong
Browse files

msm: pcie: add support for varying PCIe PHY status bit 



Status bit for PCIe PHY varies for each PCIe core. Add
the support to check the correct status bit for each
of them. Update sa8155 and sm8150 with PCIe PHY status
bit.

Change-Id: Iba583eeb3ef41c12381bee7ff2d6dd1d4cdb5fba
Signed-off-by: default avatarTony Truong <truong@codeaurora.org>
parent c14384a3

arch/arm64/boot/dts/qcom/sa6155-pcie.dtsi

+2 −1
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2018, The Linux Foundation. All rights reserved.

 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -189,6 +189,7 @@ 
		qcom,slv-addr-space-size = <0x20000000>;



		qcom,phy-status-offset = <0x974>;

		qcom,phy-status-bit = <6>;

		qcom,phy-power-down-offset = <0x804>;



		qcom,boot-option = <0x1>;

arch/arm64/boot/dts/qcom/sm8150-pcie.dtsi

+3 −1
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2018, The Linux Foundation. All rights reserved.

 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -173,6 +173,7 @@ 
		qcom,slv-addr-space-size = <0x4000000>;



		qcom,phy-status-offset = <0x814>;

		qcom,phy-status-bit = <6>;

		qcom,phy-power-down-offset = <0x840>;



		qcom,boot-option = <0x1>;
@@ -489,6 +490,7 @@ 
		qcom,slv-addr-space-size = <0x20000000>;



		qcom,phy-status-offset = <0xa14>;

		qcom,phy-status-bit = <6>;

		qcom,phy-power-down-offset = <0xa40>;



		qcom,boot-option = <0x1>;

drivers/pci/host/pci-msm.c

+20 −2
Original line number Diff line number Diff line 
/* Copyright (c) 2014-2018, The Linux Foundation. All rights reserved.

/* Copyright (c) 2014-2019, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -590,6 +590,7 @@ struct msm_pcie_dev_t { 
	uint32_t			wr_halt_size;

	uint32_t			slv_addr_space_size;

	uint32_t			phy_status_offset;

	uint32_t			phy_status_bit;

	uint32_t			phy_power_down_offset;

	uint32_t			cpl_timeout;

	uint32_t			current_bdf;
@@ -1001,7 +1002,8 @@ static void pcie_phy_init(struct msm_pcie_dev_t *dev) 


static bool pcie_phy_is_ready(struct msm_pcie_dev_t *dev)

{

	if (readl_relaxed(dev->phy + dev->phy_status_offset) & BIT(6))

	if (readl_relaxed(dev->phy + dev->phy_status_offset) &

		BIT(dev->phy_status_bit))

		return false;

	else

		return true;
@@ -1241,6 +1243,8 @@ static void msm_pcie_show_status(struct msm_pcie_dev_t *dev) 
		dev->slv_addr_space_size);

	PCIE_DBG_FS(dev, "phy_status_offset: 0x%x\n",

		dev->phy_status_offset);

	PCIE_DBG_FS(dev, "phy_status_bit: %u\n",

		dev->phy_status_bit);

	PCIE_DBG_FS(dev, "phy_power_down_offset: 0x%x\n",

		dev->phy_power_down_offset);

	PCIE_DBG_FS(dev, "cpl_timeout: 0x%x\n",
@@ -5563,6 +5567,20 @@ static int msm_pcie_probe(struct platform_device *pdev) 
			rc_idx, msm_pcie_dev[rc_idx].phy_status_offset);

	}



	ret = of_property_read_u32(pdev->dev.of_node,

				"qcom,phy-status-bit",

				&msm_pcie_dev[rc_idx].phy_status_bit);

	if (ret) {

		PCIE_ERR(&msm_pcie_dev[rc_idx],

			"RC%d: failed to get PCIe PHY status bit.\n",

			rc_idx);

		goto decrease_rc_num;

	} else {

		PCIE_DBG(&msm_pcie_dev[rc_idx],

			"RC%d: phy-status-bit: 0x%x.\n",

			rc_idx, msm_pcie_dev[rc_idx].phy_status_bit);

	}



	msm_pcie_dev[rc_idx].phy_power_down_offset = 0;

	ret = of_property_read_u32(pdev->dev.of_node,

				"qcom,phy-power-down-offset",