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Commit 8cb0a72b authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "drm/msm/dp: implementation to limit the dp link clock frequency"

parents c655f49e 63b9eaa3

drivers/gpu/drm/msm/dp/dp_panel.c

+2 −2
Original line number Original line Diff line number Diff line
@@ -1639,8 +1639,8 @@ static int dp_panel_read_dpcd(struct dp_panel *dp_panel, bool multi_func) 
	panel->minor = link_info->revision & 0x0f;

	panel->minor = link_info->revision & 0x0f;

	pr_debug("version: %d.%d\n", panel->major, panel->minor);

	pr_debug("version: %d.%d\n", panel->major, panel->minor);





	link_info->rate =

	link_info->rate = min_t(unsigned long, panel->parser->max_lclk_khz,

		drm_dp_bw_code_to_link_rate(dp_panel->dpcd[DP_MAX_LINK_RATE]);

		drm_dp_bw_code_to_link_rate(dp_panel->dpcd[DP_MAX_LINK_RATE]));

	pr_debug("link_rate=%d\n", link_info->rate);

	pr_debug("link_rate=%d\n", link_info->rate);





	link_info->num_lanes = dp_panel->dpcd[DP_MAX_LANE_COUNT] &

	link_info->num_lanes = dp_panel->dpcd[DP_MAX_LANE_COUNT] &

drivers/gpu/drm/msm/dp/dp_parser.c

+5 −0
Original line number Original line Diff line number Diff line
@@ -165,6 +165,11 @@ static int dp_parser_misc(struct dp_parser *parser) 
	if (rc)

	if (rc)

		parser->max_pclk_khz = DP_MAX_PIXEL_CLK_KHZ;

		parser->max_pclk_khz = DP_MAX_PIXEL_CLK_KHZ;





	rc = of_property_read_u32(of_node,

		"qcom,max-lclk-frequency-khz", &parser->max_lclk_khz);

	if (rc)

		parser->max_lclk_khz = DP_MAX_LINK_CLK_KHZ;



	return 0;

	return 0;

}

}

drivers/gpu/drm/msm/dp/dp_parser.h

+4 −0
Original line number Original line Diff line number Diff line
@@ -20,6 +20,7 @@ 
#define DP_LABEL "MDSS DP DISPLAY"

#define DP_LABEL "MDSS DP DISPLAY"

#define AUX_CFG_LEN	10

#define AUX_CFG_LEN	10

#define DP_MAX_PIXEL_CLK_KHZ	675000

#define DP_MAX_PIXEL_CLK_KHZ	675000

#define DP_MAX_LINK_CLK_KHZ	810000





enum dp_pm_type {

enum dp_pm_type {

	DP_CORE_PM,

	DP_CORE_PM,
@@ -190,6 +191,8 @@ static inline char *dp_phy_aux_config_type_to_string(u32 cfg_type) 
 * @mp: gpio, regulator and clock related data

 * @mp: gpio, regulator and clock related data

 * @pinctrl: pin-control related data

 * @pinctrl: pin-control related data

 * @disp_data: controller's display related data

 * @disp_data: controller's display related data

 * @max_pclk_khz: maximum pixel clock supported for the platform

 * @max_lclk_khz: maximum link clock supported for the platform

 * @hw_cfg: DP HW specific settings

 * @hw_cfg: DP HW specific settings

 * @has_mst: MST feature enable status

 * @has_mst: MST feature enable status

 * @has_mst_sideband: MST sideband feature enable status

 * @has_mst_sideband: MST sideband feature enable status
@@ -216,6 +219,7 @@ struct dp_parser { 
	u8 l_map[4];

	u8 l_map[4];

	struct dp_aux_cfg aux_cfg[AUX_CFG_LEN];

	struct dp_aux_cfg aux_cfg[AUX_CFG_LEN];

	u32 max_pclk_khz;

	u32 max_pclk_khz;

	u32 max_lclk_khz;

	struct dp_hw_cfg hw_cfg;

	struct dp_hw_cfg hw_cfg;

	bool has_mst;

	bool has_mst;

	bool has_mst_sideband;

	bool has_mst_sideband;