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Commit 63b9eaa3 authored by Sankeerth Billakanti's avatar Sankeerth Billakanti Committed by Gerrit - the friendly Code Review server
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drm/msm/dp: implementation to limit the dp link clock frequency 



Some targets like SM6150 do not support the DP link clock frequency
greater than 5.4Gbps. These changes limit the link clock frequency
support in the DP driver based on the input from DT property.

CRs-Fixed: 2372619
Change-Id: Ic76629f9d705d2b9d9e49cd5bc1137dd3ed83fc3
Signed-off-by: default avatarSankeerth Billakanti <sbillaka@codeaurora.org>
parent 352a344c

drivers/gpu/drm/msm/dp/dp_panel.c

+2 −2
Original line number Diff line number Diff line
@@ -1639,8 +1639,8 @@ static int dp_panel_read_dpcd(struct dp_panel *dp_panel, bool multi_func) 
	panel->minor = link_info->revision & 0x0f;

	pr_debug("version: %d.%d\n", panel->major, panel->minor);



	link_info->rate =

		drm_dp_bw_code_to_link_rate(dp_panel->dpcd[DP_MAX_LINK_RATE]);

	link_info->rate = min_t(unsigned long, panel->parser->max_lclk_khz,

		drm_dp_bw_code_to_link_rate(dp_panel->dpcd[DP_MAX_LINK_RATE]));

	pr_debug("link_rate=%d\n", link_info->rate);



	link_info->num_lanes = dp_panel->dpcd[DP_MAX_LANE_COUNT] &

drivers/gpu/drm/msm/dp/dp_parser.c

+5 −0
Original line number Diff line number Diff line
@@ -165,6 +165,11 @@ static int dp_parser_misc(struct dp_parser *parser) 
	if (rc)

		parser->max_pclk_khz = DP_MAX_PIXEL_CLK_KHZ;



	rc = of_property_read_u32(of_node,

		"qcom,max-lclk-frequency-khz", &parser->max_lclk_khz);

	if (rc)

		parser->max_lclk_khz = DP_MAX_LINK_CLK_KHZ;



	return 0;

}

drivers/gpu/drm/msm/dp/dp_parser.h

+4 −0
Original line number Diff line number Diff line
@@ -20,6 +20,7 @@ 
#define DP_LABEL "MDSS DP DISPLAY"

#define AUX_CFG_LEN	10

#define DP_MAX_PIXEL_CLK_KHZ	675000

#define DP_MAX_LINK_CLK_KHZ	810000



enum dp_pm_type {

	DP_CORE_PM,
@@ -190,6 +191,8 @@ static inline char *dp_phy_aux_config_type_to_string(u32 cfg_type) 
 * @mp: gpio, regulator and clock related data

 * @pinctrl: pin-control related data

 * @disp_data: controller's display related data

 * @max_pclk_khz: maximum pixel clock supported for the platform

 * @max_lclk_khz: maximum link clock supported for the platform

 * @hw_cfg: DP HW specific settings

 * @has_mst: MST feature enable status

 * @has_mst_sideband: MST sideband feature enable status
@@ -216,6 +219,7 @@ struct dp_parser { 
	u8 l_map[4];

	struct dp_aux_cfg aux_cfg[AUX_CFG_LEN];

	u32 max_pclk_khz;

	u32 max_lclk_khz;

	struct dp_hw_cfg hw_cfg;

	bool has_mst;

	bool has_mst_sideband;