Coresight: disable cache feature for tmc controller



Clean TMC_AXICTL_CACHE_CTL_B1 bit to disable cache
No need to enable this feature.

Change-Id: I984709fcbe41e7bac71646cd4fec6ada8452cfb8
Signed-off-by: Shaoqing Liu <shaoqingliu@codeaurora.org>

parent 639638f7

drivers/hwtracing/coresight/coresight-tmc-etr.c

+1 −1

Original line number	Diff line number	Diff line
		@@ -448,7 +448,7 @@ void tmc_etr_enable_hw(struct tmc_drvdata *drvdata)

		axictl = (axictl &
		~(TMC_AXICTL_CACHE_CTL_B0 \| TMC_AXICTL_CACHE_CTL_B1)) \|
		TMC_AXICTL_CACHE_CTL_B0 \| TMC_AXICTL_CACHE_CTL_B1;
		TMC_AXICTL_CACHE_CTL_B0;
		writel_relaxed(axictl, drvdata->base + TMC_AXICTL);
		tmc_write_dba(drvdata, drvdata->paddr);
		/*