Loading drivers/power/supply/qcom/qpnp-smb5.c +9 −0 Original line number Diff line number Diff line Loading @@ -1927,6 +1927,15 @@ static int smb5_init_hw(struct smb5 *chip) } } /* set the Source Mode (OTG) current limit */ rc = smblib_masked_write(chg, DCDC_OTG_CURRENT_LIMIT_CFG_REG, OTG_CURRENT_LIMIT_MASK, OTG_CURRENT_LIMIT_3000_MA); if (rc < 0) { dev_err(chg->dev, "Couldn't configure DCDC_OTG_CURRENT_LIMIT_CFG rc=%d\n", rc); return rc; } if (chg->sw_jeita_enabled) { rc = smblib_disable_hw_jeita(chg, true); if (rc < 0) { Loading drivers/power/supply/qcom/smb5-reg.h +9 −0 Original line number Diff line number Diff line Loading @@ -134,6 +134,15 @@ enum { #define DCDC_FSW_SEL_REG (DCDC_BASE + 0x50) #define DCDC_OTG_CURRENT_LIMIT_CFG_REG (DCDC_BASE + 0x52) #define OTG_CURRENT_LIMIT_MASK GENMASK(2, 0) enum { OTG_CURRENT_LIMIT_500_MA, OTG_CURRENT_LIMIT_1000_MA, OTG_CURRENT_LIMIT_1500_MA, OTG_CURRENT_LIMIT_2000_MA, OTG_CURRENT_LIMIT_2500_MA, OTG_CURRENT_LIMIT_3000_MA }; #define DCDC_OTG_CFG_REG (DCDC_BASE + 0x53) #define OTG_EN_SRC_CFG_BIT BIT(1) Loading Loading
drivers/power/supply/qcom/qpnp-smb5.c +9 −0 Original line number Diff line number Diff line Loading @@ -1927,6 +1927,15 @@ static int smb5_init_hw(struct smb5 *chip) } } /* set the Source Mode (OTG) current limit */ rc = smblib_masked_write(chg, DCDC_OTG_CURRENT_LIMIT_CFG_REG, OTG_CURRENT_LIMIT_MASK, OTG_CURRENT_LIMIT_3000_MA); if (rc < 0) { dev_err(chg->dev, "Couldn't configure DCDC_OTG_CURRENT_LIMIT_CFG rc=%d\n", rc); return rc; } if (chg->sw_jeita_enabled) { rc = smblib_disable_hw_jeita(chg, true); if (rc < 0) { Loading
drivers/power/supply/qcom/smb5-reg.h +9 −0 Original line number Diff line number Diff line Loading @@ -134,6 +134,15 @@ enum { #define DCDC_FSW_SEL_REG (DCDC_BASE + 0x50) #define DCDC_OTG_CURRENT_LIMIT_CFG_REG (DCDC_BASE + 0x52) #define OTG_CURRENT_LIMIT_MASK GENMASK(2, 0) enum { OTG_CURRENT_LIMIT_500_MA, OTG_CURRENT_LIMIT_1000_MA, OTG_CURRENT_LIMIT_1500_MA, OTG_CURRENT_LIMIT_2000_MA, OTG_CURRENT_LIMIT_2500_MA, OTG_CURRENT_LIMIT_3000_MA }; #define DCDC_OTG_CFG_REG (DCDC_BASE + 0x53) #define OTG_EN_SRC_CFG_BIT BIT(1) Loading