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Commit 85e8f8d1 authored by Koji Matsuoka's avatar Koji Matsuoka Committed by Laurent Pinchart
Browse files

drm: rcar-du: Fix LVDS start sequence on Gen3 



According to the latest revision of the datasheet, the LVDS I/O pins
must be enabled before starting the PLL. Fix it.

Signed-off-by: default avatarKoji Matsuoka <koji.matsuoka.xm@renesas.com>
Signed-off-by: default avatarLaurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
parent fd1adef3

drivers/gpu/drm/rcar-du/rcar_du_lvdsenc.c

+8 −7
Original line number Diff line number Diff line
@@ -104,7 +104,14 @@ static void rcar_du_lvdsenc_start_gen3(struct rcar_du_lvdsenc *lvds, 


	rcar_lvds_write(lvds, LVDPLLCR, pllcr);



	/* Turn the PLL on, set it to LVDS normal mode, wait for the startup

	/* Turn all the channels on. */

	rcar_lvds_write(lvds, LVDCR1,

			LVDCR1_CHSTBY_GEN3(3) | LVDCR1_CHSTBY_GEN3(2) |

			LVDCR1_CHSTBY_GEN3(1) | LVDCR1_CHSTBY_GEN3(0) |

			LVDCR1_CLKSTBY_GEN3);



	/*

	 * Turn the PLL on, set it to LVDS normal mode, wait for the startup

	 * delay and turn the output on.

	 */

	lvdcr0 = LVDCR0_PLLON;
@@ -117,12 +124,6 @@ static void rcar_du_lvdsenc_start_gen3(struct rcar_du_lvdsenc *lvds, 


	lvdcr0 |= LVDCR0_LVRES;

	rcar_lvds_write(lvds, LVDCR0, lvdcr0);



	/* Turn all the channels on. */

	rcar_lvds_write(lvds, LVDCR1,

			LVDCR1_CHSTBY_GEN3(3) | LVDCR1_CHSTBY_GEN3(2) |

			LVDCR1_CHSTBY_GEN3(1) | LVDCR1_CHSTBY_GEN3(0) |

			LVDCR1_CLKSTBY_GEN3);

}



static int rcar_du_lvdsenc_start(struct rcar_du_lvdsenc *lvds,