Merge "ARM: dts: msm: enable AHB2PHY_WEST clock during DP PLL programming"

		clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>,

			 <&clock_rpmh RPMH_CXO_CLK>,

			 <&clock_gcc GCC_AHB2PHY_WEST_CLK>,

			 <&clock_gcc GCC_DISP_AHB_CLK>,

			 <&clock_gcc GCC_USB3_SEC_CLKREF_CLK>;

		clock-names = "iface_clk", "ref_clk_src", "gcc_iface",

			"ref_clk";

		clock-names = "iface_clk", "ref_clk_src", "cfg_ahb_clk",

			"gcc_iface", "ref_clk";

		clock-rate = <0>;

		gdsc-supply = <&mdss_core_gdsc>;