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Commit 02bb73d1 authored by Padmanabhan Komanduru's avatar Padmanabhan Komanduru
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ARM: dts: msm: enable AHB2PHY_WEST clock during DP PLL programming 



AHB2PHY_WEST clock needs to be enabled to program Display Port PLL
registers for SM6150. Add the clock node for this in the SM6150 DP
PLL node to take care of this.

Change-Id: I93b778bcc05639856a2b31faed1d0d8c67e4e1aa
Signed-off-by: default avatarPadmanabhan Komanduru <pkomandu@codeaurora.org>
parent 51683be8

arch/arm64/boot/dts/qcom/sm6150-sde-pll.dtsi

+3 −2
Original line number Diff line number Diff line
@@ -55,10 +55,11 @@ 


		clocks = <&clock_dispcc DISP_CC_MDSS_AHB_CLK>,

			 <&clock_rpmh RPMH_CXO_CLK>,

			 <&clock_gcc GCC_AHB2PHY_WEST_CLK>,

			 <&clock_gcc GCC_DISP_AHB_CLK>,

			 <&clock_gcc GCC_USB3_SEC_CLKREF_CLK>;

		clock-names = "iface_clk", "ref_clk_src", "gcc_iface",

			"ref_clk";

		clock-names = "iface_clk", "ref_clk_src", "cfg_ahb_clk",

			"gcc_iface", "ref_clk";

		clock-rate = <0>;



		gdsc-supply = <&mdss_core_gdsc>;