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Commit 85ae822d authored by Diptanshu Jamgade's avatar Diptanshu Jamgade
Browse files

clk: qcom: clk-alpha-pll: Update clk_alpha_pll_ops to bypass HW postdiv 



Update clk_alpha_pll_ops to avoid post_div application in recalc_rate
ops as the present implementation applies the postdiv. Also update
clk_alpha_pll_set_rate to write the alpha value.

Change-Id: I0ae71687d80b1488475b40f45272ce6aa8de6fc0
Signed-off-by: default avatarDiptanshu Jamgade <djamgade@codeaurora.org>
parent 9bd66533

drivers/clk/qcom/clk-alpha-pll.c

+2 −4
Original line number Diff line number Diff line
@@ -569,10 +569,7 @@ clk_alpha_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) 
		}

	}



	ctl >>= PLL_POST_DIV_SHIFT;

	ctl &= PLL_POST_DIV_MASK;



	return alpha_pll_calc_rate(pll, prate, l, a) >> fls(ctl);

	return alpha_pll_calc_rate(pll, prate, l, a);

}



static int clk_alpha_pll_dynamic_update(struct clk_alpha_pll *pll)
@@ -660,6 +657,7 @@ static int clk_alpha_pll_set_rate(struct clk_hw *hw, unsigned long rate, 
			     a & ALPHA_16BIT_MASK);

	} else {

		a <<= (ALPHA_REG_BITWIDTH - ALPHA_BITWIDTH);

		regmap_write(pll->clkr.regmap, off + PLL_ALPHA_VAL, a);

		regmap_write(pll->clkr.regmap, off + PLL_ALPHA_VAL_U, a >> 32);

	}