Loading drivers/phy/qualcomm/phy-qcom-ufs-qmp-v4.h +7 −3 Original line number Diff line number Diff line Loading @@ -129,6 +129,7 @@ #define QSERDES_RX0_AC_JTAG_ENABLE RX_OFF(0, 0x68) #define QSERDES_RX0_UCDR_FO_GAIN RX_OFF(0, 0x08) #define QSERDES_RX0_UCDR_SO_GAIN RX_OFF(0, 0x14) #define QSERDES_RX0_AC_JTAG_MODE RX_OFF(0, 0x78) #define QSERDES_RX1_SIGDET_LVL RX_OFF(1, 0x120) #define QSERDES_RX1_SIGDET_CNTRL RX_OFF(1, 0x11C) Loading Loading @@ -165,6 +166,7 @@ #define QSERDES_RX1_AC_JTAG_ENABLE RX_OFF(1, 0x68) #define QSERDES_RX1_UCDR_FO_GAIN RX_OFF(1, 0x08) #define QSERDES_RX1_UCDR_SO_GAIN RX_OFF(1, 0x14) #define QSERDES_RX1_AC_JTAG_MODE RX_OFF(1, 0x78) #define UFS_PHY_RX_LINECFG_DISABLE_BIT BIT(1) Loading Loading @@ -245,7 +247,7 @@ static struct ufs_qcom_phy_calibration phy_cal_table_rate_A[] = { UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_10_HIGH3, 0x3B), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_10_HIGH4, 0xB1), UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_MIN_HIBERN8_TIME, 0xFF), UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL2, 0x6F), UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL2, 0x6D), UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_DRV_LVL, 0x0A), UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_SMALL_AMP_DRV_LVL, 0x02), UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_MID_TERM_CTRL1, 0x43), Loading @@ -257,7 +259,8 @@ static struct ufs_qcom_phy_calibration phy_cal_table_rate_A[] = { UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_HS_GEAR_BAND, 0x06), UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_HSGEAR_CAPABILITY, 0x03), UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_HSGEAR_CAPABILITY, 0x03), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_AC_JTAG_ENABLE, 0x00), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_AC_JTAG_ENABLE, 0x01), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_AC_JTAG_MODE, 0x01), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FO_GAIN, 0x0C), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SO_GAIN, 0x04), }; Loading Loading @@ -302,7 +305,8 @@ static struct ufs_qcom_phy_calibration phy_cal_table_2nd_lane[] = { UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_10_HIGH3, 0x3B), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_10_HIGH4, 0xB1), UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_MULTI_LANE_CTRL1, 0x02), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_AC_JTAG_ENABLE, 0x00), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_AC_JTAG_ENABLE, 0x01), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_AC_JTAG_MODE, 0x01), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_FO_GAIN, 0x0C), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_SO_GAIN, 0x04), }; Loading Loading
drivers/phy/qualcomm/phy-qcom-ufs-qmp-v4.h +7 −3 Original line number Diff line number Diff line Loading @@ -129,6 +129,7 @@ #define QSERDES_RX0_AC_JTAG_ENABLE RX_OFF(0, 0x68) #define QSERDES_RX0_UCDR_FO_GAIN RX_OFF(0, 0x08) #define QSERDES_RX0_UCDR_SO_GAIN RX_OFF(0, 0x14) #define QSERDES_RX0_AC_JTAG_MODE RX_OFF(0, 0x78) #define QSERDES_RX1_SIGDET_LVL RX_OFF(1, 0x120) #define QSERDES_RX1_SIGDET_CNTRL RX_OFF(1, 0x11C) Loading Loading @@ -165,6 +166,7 @@ #define QSERDES_RX1_AC_JTAG_ENABLE RX_OFF(1, 0x68) #define QSERDES_RX1_UCDR_FO_GAIN RX_OFF(1, 0x08) #define QSERDES_RX1_UCDR_SO_GAIN RX_OFF(1, 0x14) #define QSERDES_RX1_AC_JTAG_MODE RX_OFF(1, 0x78) #define UFS_PHY_RX_LINECFG_DISABLE_BIT BIT(1) Loading Loading @@ -245,7 +247,7 @@ static struct ufs_qcom_phy_calibration phy_cal_table_rate_A[] = { UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_10_HIGH3, 0x3B), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_RX_MODE_10_HIGH4, 0xB1), UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_MIN_HIBERN8_TIME, 0xFF), UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL2, 0x6F), UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_SIGDET_CTRL2, 0x6D), UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_LARGE_AMP_DRV_LVL, 0x0A), UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_SMALL_AMP_DRV_LVL, 0x02), UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_MID_TERM_CTRL1, 0x43), Loading @@ -257,7 +259,8 @@ static struct ufs_qcom_phy_calibration phy_cal_table_rate_A[] = { UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_HS_GEAR_BAND, 0x06), UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_TX_HSGEAR_CAPABILITY, 0x03), UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_RX_HSGEAR_CAPABILITY, 0x03), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_AC_JTAG_ENABLE, 0x00), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_AC_JTAG_ENABLE, 0x01), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_AC_JTAG_MODE, 0x01), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_FO_GAIN, 0x0C), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX0_UCDR_SO_GAIN, 0x04), }; Loading Loading @@ -302,7 +305,8 @@ static struct ufs_qcom_phy_calibration phy_cal_table_2nd_lane[] = { UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_10_HIGH3, 0x3B), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_RX_MODE_10_HIGH4, 0xB1), UFS_QCOM_PHY_CAL_ENTRY(UFS_PHY_MULTI_LANE_CTRL1, 0x02), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_AC_JTAG_ENABLE, 0x00), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_AC_JTAG_ENABLE, 0x01), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_AC_JTAG_MODE, 0x01), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_FO_GAIN, 0x0C), UFS_QCOM_PHY_CAL_ENTRY(QSERDES_RX1_UCDR_SO_GAIN, 0x04), }; Loading