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Commit 84c0fdbc authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge changes I323c6d1b,I54e0f673,I8a2b6f58,Icdf35cb2 into msm-4.14 

* changes:
  drm/msm/sde: update blob property to expose secure-ui supported blendstage
  drm/msm/sde: avoid detaching non-sec context bank during secure-ui
  ARM: dts: msm: add secure-sid masks for sdm855 target
  drm/msm/sde: add parsing logic for sec_sid_mask
parents d0137830 9989563e

Documentation/devicetree/bindings/display/msm/sde.txt

+3 −0
Original line number Diff line number Diff line
@@ -405,6 +405,8 @@ Optional properties: 
				control register. Number of offsets defined should

				match the number of xin-ids defined in

				property: qcom,sde-inline-rot-xin

- qcom,sde-secure-sid-mask:	Array of secure SID masks used during

				secure-camera/secure-display usecases.

- #power-domain-cells:		Number of cells in a power-domain specifier and should contain 0.

- qcom,sde-mixer-display-pref:  A string array indicating the preferred display type

				for the mixer block. Possible values:
@@ -681,6 +683,7 @@ Example: 
    qcom,sde-max-per-pipe-bw-kbps = <2400000 2400000 2400000 2400000

        2400000 2400000 2400000 2400000>;

    qcom,sde-amortizable-threshold = <11>;

    qcom,sde-secure-sid-mask = <0x200801 0x200c01>;



    qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>;

    qcom,sde-vbif-qos-nrt-remap = <3 3 3 3 3 3 3 3>;

arch/arm64/boot/dts/qcom/sdm855-sde.dtsi

+2 −0
Original line number Diff line number Diff line
@@ -221,6 +221,8 @@ 
		qcom,sde-reg-dma-version = <0x00010001>;

		qcom,sde-reg-dma-trigger-off = <0x119c>;



		qcom,sde-secure-sid-mask = <0x4200801>;



		qcom,sde-sspp-vig-blocks {

			qcom,sde-vig-csc-off = <0x1a00>;

			qcom,sde-vig-qseed-off = <0xa00>;

drivers/gpu/drm/msm/sde/sde_crtc.c

+111 −62
Original line number Diff line number Diff line
@@ -1805,15 +1805,9 @@ int sde_crtc_get_secure_transition_ops(struct drm_crtc *crtc, 
	secure_level = sde_crtc_get_secure_level(crtc, crtc->state);

	catalog = sde_kms->catalog;



	SDE_DEBUG("crtc%d, secure_level%d old_valid_fb%d\n",

			crtc->base.id, secure_level, old_valid_fb);



	SDE_EVT32_VERBOSE(DRMID(crtc), secure_level, smmu_state->state,

			old_valid_fb, SDE_EVTLOG_FUNC_ENTRY);

	/**

	 * SMMU operations need to be delayed in case of

	 * video mode panels when switching back to non_secure

	 * mode

	/*

	 * SMMU operations need to be delayed in case of video mode panels

	 * when switching back to non_secure mode

	 */

	drm_for_each_encoder(encoder, crtc->dev) {

		if (encoder->crtc != crtc)
@@ -1823,6 +1817,11 @@ int sde_crtc_get_secure_transition_ops(struct drm_crtc *crtc, 
						MSM_DISPLAY_CAP_VID_MODE);

	}



	SDE_DEBUG("crtc%d: secure_level %d old_valid_fb %d post_commit %d\n",

			DRMID(crtc), secure_level, old_valid_fb, post_commit);

	SDE_EVT32_VERBOSE(DRMID(crtc), secure_level, smmu_state->state,

			old_valid_fb, post_commit, SDE_EVTLOG_FUNC_ENTRY);



	drm_atomic_crtc_for_each_plane(plane, crtc) {

		if (!plane->state)

			continue;
@@ -1831,15 +1830,12 @@ int sde_crtc_get_secure_transition_ops(struct drm_crtc *crtc, 
				to_sde_plane_state(plane->state),

				PLANE_PROP_FB_TRANSLATION_MODE);

		if (translation_mode > SDE_DRM_FB_SEC_DIR_TRANS) {

			SDE_ERROR("crtc%d, invalid translation_mode%d\n",

					crtc->base.id, translation_mode);

			SDE_ERROR("crtc%d: invalid translation_mode %d\n",

					DRMID(crtc), translation_mode);

			return -EINVAL;

		}



		/**

		 * we can break if we find sec_fir or non_sec_dir

		 * plane

		 */

		/* we can break if we find sec_dir plane */

		if (translation_mode == SDE_DRM_FB_SEC_DIR_TRANS)

			break;

	}
@@ -1849,21 +1845,23 @@ int sde_crtc_get_secure_transition_ops(struct drm_crtc *crtc, 
	switch (translation_mode) {

	case SDE_DRM_FB_SEC_DIR_TRANS:

		/* secure display usecase */

		if ((smmu_state->state == ATTACHED) &&

				(secure_level == SDE_DRM_SEC_ONLY)) {

			smmu_state->state = DETACH_ALL_REQ;

		if ((smmu_state->state == ATTACHED)

				&& (secure_level == SDE_DRM_SEC_ONLY)) {

			smmu_state->state = catalog->sui_ns_allowed ?

						DETACH_SEC_REQ : DETACH_ALL_REQ;

			smmu_state->secure_level = secure_level;

			smmu_state->transition_type = PRE_COMMIT;

			ops |= SDE_KMS_OPS_SECURE_STATE_CHANGE;

			if (old_valid_fb) {

			if (old_valid_fb)

				ops |= (SDE_KMS_OPS_WAIT_FOR_TX_DONE  |

						SDE_KMS_OPS_CLEANUP_PLANE_FB);

			}

			if (catalog->sui_misr_supported)

				smmu_state->sui_misr_state =

						SUI_MISR_ENABLE_REQ;

		/* secure camera usecase */

		} else if (smmu_state->state == ATTACHED) {

			smmu_state->state = DETACH_SEC_REQ;

			smmu_state->secure_level = secure_level;

			smmu_state->transition_type = PRE_COMMIT;

			ops |= SDE_KMS_OPS_SECURE_STATE_CHANGE;

		}
@@ -1871,17 +1869,14 @@ int sde_crtc_get_secure_transition_ops(struct drm_crtc *crtc, 


	case SDE_DRM_FB_SEC:

	case SDE_DRM_FB_NON_SEC:

		if ((smmu_state->state == DETACHED_SEC) ||

			(smmu_state->state == DETACH_SEC_REQ)) {

			smmu_state->state = ATTACH_SEC_REQ;

			smmu_state->transition_type = post_commit ?

				POST_COMMIT : PRE_COMMIT;

			ops |= SDE_KMS_OPS_SECURE_STATE_CHANGE;

			if (old_valid_fb)

				ops |= SDE_KMS_OPS_WAIT_FOR_TX_DONE;

		} else if ((smmu_state->state == DETACHED) ||

				(smmu_state->state == DETACH_ALL_REQ)) {

			smmu_state->state = ATTACH_ALL_REQ;

		if (((smmu_state->state == DETACHED)

				|| (smmu_state->state == DETACH_ALL_REQ))

			|| ((smmu_state->secure_level == SDE_DRM_SEC_ONLY)

				&& ((smmu_state->state == DETACHED_SEC)

				  || (smmu_state->state == DETACH_SEC_REQ)))) {

			smmu_state->state = catalog->sui_ns_allowed ?

						ATTACH_SEC_REQ : ATTACH_ALL_REQ;

			smmu_state->secure_level = secure_level;

			smmu_state->transition_type = post_commit ?

						POST_COMMIT : PRE_COMMIT;

			ops |= SDE_KMS_OPS_SECURE_STATE_CHANGE;
@@ -1891,21 +1886,35 @@ int sde_crtc_get_secure_transition_ops(struct drm_crtc *crtc, 
			if (catalog->sui_misr_supported)

				smmu_state->sui_misr_state =

						SUI_MISR_DISABLE_REQ;

		} else if ((smmu_state->state == DETACHED_SEC)

				|| (smmu_state->state == DETACH_SEC_REQ)) {

			smmu_state->state = ATTACH_SEC_REQ;

			smmu_state->secure_level = secure_level;

			smmu_state->transition_type = post_commit ?

						POST_COMMIT : PRE_COMMIT;

			ops |= SDE_KMS_OPS_SECURE_STATE_CHANGE;

			if (old_valid_fb)

				ops |= SDE_KMS_OPS_WAIT_FOR_TX_DONE;

		}

		break;



	default:

		SDE_ERROR("invalid plane fb_mode:%d\n", translation_mode);

		SDE_ERROR("crtc%d: invalid plane fb_mode %d\n",

				DRMID(crtc), translation_mode);

		ops = -EINVAL;

	}



	SDE_DEBUG("SMMU State:%d, type:%d ops:%x\n", smmu_state->state,

			smmu_state->transition_type, ops);

	/* log only during actual transition times */

	if (ops)

	if (ops) {

		SDE_DEBUG("crtc%d: state %d, secure_level %d, type %d ops %x\n",

			DRMID(crtc), smmu_state->state,

			smmu_state->secure_level,

			smmu_state->transition_type, ops);

		SDE_EVT32(DRMID(crtc), secure_level, translation_mode,

				smmu_state->state, smmu_state->transition_type,

				ops, old_valid_fb, SDE_EVTLOG_FUNC_EXIT);

				smmu_state->secure_level, old_valid_fb,

				post_commit, ops, SDE_EVTLOG_FUNC_EXIT);

	}



	mutex_unlock(&sde_kms->secure_transition_lock);
@@ -3106,7 +3115,7 @@ static void sde_crtc_atomic_begin(struct drm_crtc *crtc, 
	 * apply color processing properties only if

	 * smmu state is attached,

	 */

	if (!sde_kms_is_secure_session_inprogress(sde_kms))

	if (sde_kms_is_cp_operation_allowed(sde_kms))

		sde_cp_crtc_apply_properties(crtc);



	/*
@@ -4431,7 +4440,7 @@ static int _sde_crtc_check_secure_state(struct drm_crtc *crtc, 
	}



	sde_kms = _sde_crtc_get_kms(crtc);

	if (!sde_kms) {

	if (!sde_kms || !sde_kms->catalog) {

		SDE_ERROR("invalid kms\n");

		return -EINVAL;

	}
@@ -4455,7 +4464,7 @@ static int _sde_crtc_check_secure_state(struct drm_crtc *crtc, 
		if (fb_ns || fb_sec) {

			SDE_ERROR(

			 "crtc%d: invalid fb_modes Sec:%d, NS:%d, Sec_Dir:%d\n",

				crtc->base.id, fb_sec, fb_ns, fb_sec_dir);

				DRMID(crtc), fb_sec, fb_ns, fb_sec_dir);

			return -EINVAL;

		}
@@ -4467,25 +4476,58 @@ static int _sde_crtc_check_secure_state(struct drm_crtc *crtc, 
			if (!pstates[i].drm_pstate

					|| !pstates[i].drm_pstate->plane) {

				SDE_ERROR("crtc%d: invalid pstate at i:%d\n",

						crtc->base.id, i);

						DRMID(crtc), i);

				return -EINVAL;

			}

			plane = pstates[i].drm_pstate->plane;



			if (!sde_plane_is_sec_ui_allowed(plane)) {

				SDE_ERROR("crtc%d: sec-ui not allowed in p%d\n",

						crtc->base.id, plane->base.id);

						DRMID(crtc), plane->base.id);

				return -EINVAL;

			}



			if (pstates[i].stage != pstates[i-1].stage) {

			} else if (pstates[i].stage != pstates[i-1].stage) {

				SDE_ERROR(

				  "crtc%d: invalid blend stages %d:%d, %d:%d\n",

				  crtc->base.id, i, pstates[i].stage,

				  DRMID(crtc), i, pstates[i].stage,

				  i-1, pstates[i-1].stage);

				return -EINVAL;

			}

		}



		/* check if all the dim_layers are in the same stage */

		for (i = 1; i < cstate->num_dim_layers; i++) {

			if (cstate->dim_layer[i].stage !=

					cstate->dim_layer[i-1].stage) {

				SDE_ERROR(

				"crtc%d: invalid dimlayer stage %d:%d, %d:%d\n",

					DRMID(crtc),

					i, cstate->dim_layer[i].stage,

					i-1, cstate->dim_layer[i-1].stage);

				return -EINVAL;

			}

		}



		/*

		 * if secure-ui supported blendstage is specified,

		 * - fail empty commit

		 * - validate dim_layer or plane is staged in the supported

		 *   blendstage

		 */

		if (sde_kms->catalog->sui_supported_blendstage) {

			int sec_stage = cnt ? pstates[0].sde_pstate->stage :

						cstate->dim_layer[0].stage;



			if ((!cnt && !cstate->num_dim_layers) ||

				(sde_kms->catalog->sui_supported_blendstage

						!= (sec_stage - SDE_STAGE_0))) {

				SDE_ERROR(

				  "crtc%d: empty cnt%d/dim%d or bad stage%d\n",

					DRMID(crtc), cnt,

					cstate->num_dim_layers, sec_stage);

				return -EINVAL;

			}

		}

	}



	/*
@@ -4499,7 +4541,7 @@ static int _sde_crtc_check_secure_state(struct drm_crtc *crtc, 


		if (encoder_cnt > MAX_ALLOWED_ENCODER_CNT_PER_SECURE_CRTC) {

			SDE_ERROR("crtc%d, invalid virtual encoder crtc%d\n",

				crtc->base.id, encoder_cnt);

				DRMID(crtc), encoder_cnt);

			return -EINVAL;



		}
@@ -4524,18 +4566,23 @@ static int _sde_crtc_check_secure_state(struct drm_crtc *crtc, 
		((fb_sec_dir && ((smmu_state->state == ATTACHED) &&

			(secure == SDE_DRM_SEC_ONLY))) ||

		    (fb_ns && ((smmu_state->state == DETACHED) ||

				(smmu_state->state == DETACH_ALL_REQ))))) {



		SDE_EVT32(DRMID(&sde_crtc->base), fb_ns, fb_sec_dir,

		  smmu_state->state, crtc->state->plane_mask,

			crtc->state->plane_mask);

		SDE_DEBUG("crtc %d, Invalid secure transition %x\n",

				crtc->base.id, smmu_state->state);

			(smmu_state->state == DETACH_ALL_REQ))) ||

		    (fb_ns && ((smmu_state->state == DETACHED_SEC) ||

			(smmu_state->state == DETACH_SEC_REQ)) &&

			(smmu_state->secure_level == SDE_DRM_SEC_ONLY)))) {



		SDE_EVT32(DRMID(crtc), fb_ns, fb_sec_dir,

			smmu_state->state, smmu_state->secure_level,

			secure, crtc->state->plane_mask, state->plane_mask);

		SDE_ERROR(

		 "crtc%d Invalid transition;sec%d state%d slvl%d ns%d sdir%d\n",

			DRMID(crtc), secure, smmu_state->state,

			smmu_state->secure_level, fb_ns, fb_sec_dir);

		return -EINVAL;



	}



	SDE_DEBUG("crtc:%d Secure validation successful\n", crtc->base.id);

	SDE_DEBUG("crtc:%d Secure validation successful\n", DRMID(crtc));



	return 0;

}
@@ -4704,10 +4751,6 @@ static int sde_crtc_atomic_check(struct drm_crtc *crtc, 
	/* assign mixer stages based on sorted zpos property */

	sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL);



	rc = _sde_crtc_check_secure_state(crtc, state, pstates, cnt);

	if (rc)

		goto end;



	rc = _sde_crtc_excl_dim_layer_check(state, pstates, cnt);

	if (rc)

		goto end;
@@ -4773,6 +4816,10 @@ static int sde_crtc_atomic_check(struct drm_crtc *crtc, 
		}

	}



	rc = _sde_crtc_check_secure_state(crtc, state, pstates, cnt);

	if (rc)

		goto end;



	rc = sde_core_perf_crtc_check(crtc, state);

	if (rc) {

		SDE_ERROR("crtc%d failed performance check %d\n",
@@ -5111,6 +5158,8 @@ static void sde_crtc_install_properties(struct drm_crtc *crtc, 
			catalog->perf.amortizable_threshold);

	sde_kms_info_add_keyint(info, "min_prefill_lines",

			catalog->perf.min_prefill_lines);

	sde_kms_info_add_keyint(info, "sec_ui_blendstage",

			catalog->sui_supported_blendstage);



	if (catalog->ubwc_bw_calc_version)

		sde_kms_info_add_keyint(info, "ubwc_bw_calc_ver",

drivers/gpu/drm/msm/sde/sde_hw_catalog.c

+15 −1
Original line number Diff line number Diff line
@@ -167,6 +167,7 @@ enum sde_prop { 
	MACROTILE_MODE,

	UBWC_BW_CALC_VERSION,

	PIPE_ORDER_VERSION,

	SEC_SID_MASK,

	SDE_PROP_MAX,

};
@@ -442,6 +443,7 @@ static struct sde_prop_type sde_prop[] = { 
			PROP_TYPE_U32},

	{PIPE_ORDER_VERSION, "qcom,sde-pipe-order-version", false,

			PROP_TYPE_U32},

	{SEC_SID_MASK, "qcom,sde-secure-sid-mask", false, PROP_TYPE_U32_ARRAY},

};



static struct sde_prop_type sde_perf_prop[] = {
@@ -2861,7 +2863,7 @@ static int sde_pp_parse_dt(struct device_node *np, struct sde_mdss_cfg *sde_cfg) 


static int sde_parse_dt(struct device_node *np, struct sde_mdss_cfg *cfg)

{

	int rc, dma_rc, len, prop_count[SDE_PROP_MAX];

	int rc, i, dma_rc, len, prop_count[SDE_PROP_MAX];

	struct sde_prop_value *prop_value = NULL;

	bool prop_exists[SDE_PROP_MAX];

	const char *type;
@@ -2885,6 +2887,11 @@ static int sde_parse_dt(struct device_node *np, struct sde_mdss_cfg *cfg) 
	if (rc)

		goto end;



	rc = _validate_dt_entry(np, &sde_prop[SEC_SID_MASK], 1,

				&prop_count[SEC_SID_MASK], NULL);

	if (rc)

		goto end;



	rc = _read_dt_entry(np, sde_prop, ARRAY_SIZE(sde_prop), prop_count,

		prop_exists, prop_value);

	if (rc)
@@ -2960,6 +2967,13 @@ static int sde_parse_dt(struct device_node *np, struct sde_mdss_cfg *cfg) 
	if (major_version < SDE_HW_MAJOR(SDE_HW_VER_500))

		set_bit(SDE_MDP_VSYNC_SEL, &cfg->mdp[0].features);



	if (prop_exists[SEC_SID_MASK]) {

		cfg->sec_sid_mask_count = prop_count[SEC_SID_MASK];

		for (i = 0; i < cfg->sec_sid_mask_count; i++)

			cfg->sec_sid_mask[i] =

				PROP_VALUE_ACCESS(prop_value, SEC_SID_MASK, i);

	}



	rc = of_property_read_string(np, sde_prop[QSEED_TYPE].prop_name, &type);

	if (!rc && !strcmp(type, "qseedv3")) {

		cfg->qseed_type = SDE_SSPP_SCALER_QSEED3;

drivers/gpu/drm/msm/sde/sde_hw_catalog.h

+11 −0
Original line number Diff line number Diff line
@@ -1040,6 +1040,12 @@ struct sde_perf_cfg { 
 * @sui_misr_supported  indicate if secure-ui-misr is supported

 * @sui_block_xin_mask  mask of all the xin-clients to be blocked during

 *                         secure-ui when secure-ui-misr feature is supported

 * @sec_sid_mask_count  number of SID masks

 * @sec_sid_mask        SID masks used during the scm_call for transition

 *                         between secure/non-secure sessions

 * @sui_ns_allowed      flag to indicate non-secure context banks are allowed

 *                         during secure-ui session

 * @sui_supported_blendstage  secure-ui supported blendstage

 */

struct sde_mdss_cfg {

	u32 hwversion;
@@ -1078,6 +1084,11 @@ struct sde_mdss_cfg { 
	bool sui_misr_supported;

	u32 sui_block_xin_mask;



	u32 sec_sid_mask_count;

	u32 sec_sid_mask[MAX_BLOCKS];

	u32 sui_ns_allowed;

	u32 sui_supported_blendstage;



	bool has_hdr;

	u32 mdss_count;

	struct sde_mdss_base_cfg mdss[MAX_BLOCKS];