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Commit 9989563e authored by Veera Sundaram Sankaran's avatar Veera Sundaram Sankaran
Browse files

drm/msm/sde: update blob property to expose secure-ui supported blendstage 



Update the crtc blob property to expose the secure-ui supported
blendstage to user-mode, which is derived from the target specific
capabilities. Add necessary driver level checks to ensure secure-ui
layers are staged only in the supported blendstage. Fail empty
commits during secure-ui session as that might result in underruns.

Change-Id: I323c6d1bc1bf2598989998ee36f299a41b97fbb2
Signed-off-by: default avatarVeera Sundaram Sankaran <veeras@codeaurora.org>
parent addca914

drivers/gpu/drm/msm/sde/sde_crtc.c

+28 −5
Original line number Diff line number Diff line
@@ -4440,7 +4440,7 @@ static int _sde_crtc_check_secure_state(struct drm_crtc *crtc, 
	}



	sde_kms = _sde_crtc_get_kms(crtc);

	if (!sde_kms) {

	if (!sde_kms || !sde_kms->catalog) {

		SDE_ERROR("invalid kms\n");

		return -EINVAL;

	}
@@ -4507,6 +4507,27 @@ static int _sde_crtc_check_secure_state(struct drm_crtc *crtc, 
				return -EINVAL;

			}

		}



		/*

		 * if secure-ui supported blendstage is specified,

		 * - fail empty commit

		 * - validate dim_layer or plane is staged in the supported

		 *   blendstage

		 */

		if (sde_kms->catalog->sui_supported_blendstage) {

			int sec_stage = cnt ? pstates[0].sde_pstate->stage :

						cstate->dim_layer[0].stage;



			if ((!cnt && !cstate->num_dim_layers) ||

				(sde_kms->catalog->sui_supported_blendstage

						!= (sec_stage - SDE_STAGE_0))) {

				SDE_ERROR(

				  "crtc%d: empty cnt%d/dim%d or bad stage%d\n",

					DRMID(crtc), cnt,

					cstate->num_dim_layers, sec_stage);

				return -EINVAL;

			}

		}

	}



	/*
@@ -4730,10 +4751,6 @@ static int sde_crtc_atomic_check(struct drm_crtc *crtc, 
	/* assign mixer stages based on sorted zpos property */

	sort(pstates, cnt, sizeof(pstates[0]), pstate_cmp, NULL);



	rc = _sde_crtc_check_secure_state(crtc, state, pstates, cnt);

	if (rc)

		goto end;



	rc = _sde_crtc_excl_dim_layer_check(state, pstates, cnt);

	if (rc)

		goto end;
@@ -4799,6 +4816,10 @@ static int sde_crtc_atomic_check(struct drm_crtc *crtc, 
		}

	}



	rc = _sde_crtc_check_secure_state(crtc, state, pstates, cnt);

	if (rc)

		goto end;



	rc = sde_core_perf_crtc_check(crtc, state);

	if (rc) {

		SDE_ERROR("crtc%d failed performance check %d\n",
@@ -5137,6 +5158,8 @@ static void sde_crtc_install_properties(struct drm_crtc *crtc, 
			catalog->perf.amortizable_threshold);

	sde_kms_info_add_keyint(info, "min_prefill_lines",

			catalog->perf.min_prefill_lines);

	sde_kms_info_add_keyint(info, "sec_ui_blendstage",

			catalog->sui_supported_blendstage);



	if (catalog->ubwc_bw_calc_version)

		sde_kms_info_add_keyint(info, "ubwc_bw_calc_ver",

drivers/gpu/drm/msm/sde/sde_hw_catalog.h

+2 −0
Original line number Diff line number Diff line
@@ -1045,6 +1045,7 @@ struct sde_perf_cfg { 
 *                         between secure/non-secure sessions

 * @sui_ns_allowed      flag to indicate non-secure context banks are allowed

 *                         during secure-ui session

 * @sui_supported_blendstage  secure-ui supported blendstage

 */

struct sde_mdss_cfg {

	u32 hwversion;
@@ -1086,6 +1087,7 @@ struct sde_mdss_cfg { 
	u32 sec_sid_mask_count;

	u32 sec_sid_mask[MAX_BLOCKS];

	u32 sui_ns_allowed;

	u32 sui_supported_blendstage;



	bool has_hdr;

	u32 mdss_count;