Loading arch/arm64/include/asm/cputype.h +2 −0 Original line number Diff line number Diff line Loading @@ -130,6 +130,8 @@ #define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL) #define MIDR_KRYO2XX_GOLD \ MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, ARM_CPU_PART_KRYO2XX_GOLD) #define MIDR_KRYO2XX_SILVER \ MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, ARM_CPU_PART_KRYO2XX_SILVER) #ifndef __ASSEMBLY__ Loading arch/arm64/kernel/cpu_errata.c +6 −0 Original line number Diff line number Diff line Loading @@ -432,6 +432,12 @@ const struct arm64_cpu_capabilities arm64_errata[] = { .capability = ARM64_WORKAROUND_845719, MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x04), }, { /* Kryo2xx Silver rAp4 */ .desc = "Kryo2xx Silver erratum 845719", .capability = ARM64_WORKAROUND_845719, MIDR_RANGE(MIDR_KRYO2XX_SILVER, 0xA00004, 0xA00004), }, #endif #ifdef CONFIG_CAVIUM_ERRATUM_23154 { Loading Loading
arch/arm64/include/asm/cputype.h +2 −0 Original line number Diff line number Diff line Loading @@ -130,6 +130,8 @@ #define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL) #define MIDR_KRYO2XX_GOLD \ MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, ARM_CPU_PART_KRYO2XX_GOLD) #define MIDR_KRYO2XX_SILVER \ MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, ARM_CPU_PART_KRYO2XX_SILVER) #ifndef __ASSEMBLY__ Loading
arch/arm64/kernel/cpu_errata.c +6 −0 Original line number Diff line number Diff line Loading @@ -432,6 +432,12 @@ const struct arm64_cpu_capabilities arm64_errata[] = { .capability = ARM64_WORKAROUND_845719, MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x04), }, { /* Kryo2xx Silver rAp4 */ .desc = "Kryo2xx Silver erratum 845719", .capability = ARM64_WORKAROUND_845719, MIDR_RANGE(MIDR_KRYO2XX_SILVER, 0xA00004, 0xA00004), }, #endif #ifdef CONFIG_CAVIUM_ERRATUM_23154 { Loading