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Commit 89bf8eea authored by Trilok Soni's avatar Trilok Soni Committed by Gaurav Kohli
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arm64: errata: Enable #845719 Errataum for Kryo2xx Silver 



Errata#845719 is also applicable for Kryo2xx Silver. Enable
the appropriate entry for it with rAp4 revision.

Please note that default midr_range logic depends on the
less or greather than logic with "min" and "max" range,
assuming that rX where X will be zero only. This is not
true for all the processors and since it is 4-bit field
it can be greater than the the "max" or pY bits.

We are specifying the direct match values like
0xA00004 instead here to keep the logic consistent.

Change-Id: I16b0c2106ae649b8a23b7ebb534c967aebd72774
Signed-off-by: default avatarTrilok Soni <tsoni@codeaurora.org>
Signed-off-by: default avatarGaurav Kohli <gkohli@codeaurora.org>
parent 2913cfe3

arch/arm64/include/asm/cputype.h

+2 −0
Original line number Diff line number Diff line
@@ -130,6 +130,8 @@ 
#define MIDR_NVIDIA_CARMEL MIDR_CPU_MODEL(ARM_CPU_IMP_NVIDIA, NVIDIA_CPU_PART_CARMEL)

#define MIDR_KRYO2XX_GOLD \

	MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, ARM_CPU_PART_KRYO2XX_GOLD)

#define MIDR_KRYO2XX_SILVER \

	MIDR_CPU_MODEL(ARM_CPU_IMP_QCOM, ARM_CPU_PART_KRYO2XX_SILVER)



#ifndef __ASSEMBLY__

arch/arm64/kernel/cpu_errata.c

+6 −0
Original line number Diff line number Diff line
@@ -432,6 +432,12 @@ const struct arm64_cpu_capabilities arm64_errata[] = { 
		.capability = ARM64_WORKAROUND_845719,

		MIDR_RANGE(MIDR_CORTEX_A53, 0x00, 0x04),

	},

	{

	/* Kryo2xx Silver rAp4 */

		.desc = "Kryo2xx Silver erratum 845719",

		.capability = ARM64_WORKAROUND_845719,

		MIDR_RANGE(MIDR_KRYO2XX_SILVER, 0xA00004, 0xA00004),

	},

#endif

#ifdef CONFIG_CAVIUM_ERRATUM_23154

	{