Loading drivers/gpu/drm/msm/sde/sde_encoder_phys_vid.c +12 −1 Original line number Diff line number Diff line Loading @@ -216,16 +216,27 @@ static void programmable_fetch_config(struct sde_encoder_phys *phys_enc, u32 vert_total = 0; u32 vfp_fetch_start_vsync_counter = 0; unsigned long lock_flags; struct sde_mdss_cfg *m; if (WARN_ON_ONCE(!phys_enc->hw_intf->ops.setup_prg_fetch)) return; m = phys_enc->sde_kms->catalog; vfp_fetch_lines = programmable_fetch_get_num_lines(vid_enc, timing); if (vfp_fetch_lines) { vert_total = get_vertical_total(timing); horiz_total = get_horizontal_total(timing); vfp_fetch_start_vsync_counter = (vert_total - vfp_fetch_lines) * horiz_total + 1; /** * Check if we need to throttle the fetch to start * from second line after the active region. */ if (m->delay_prg_fetch_start) vfp_fetch_start_vsync_counter += horiz_total; f.enable = 1; f.fetch_start = vfp_fetch_start_vsync_counter; } Loading drivers/gpu/drm/msm/sde/sde_hw_catalog.c +1 −0 Original line number Diff line number Diff line Loading @@ -3517,6 +3517,7 @@ static int _sde_hardware_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev) sde_cfg->vbif_qos_nlvl = 8; sde_cfg->ts_prefill_rev = 2; sde_cfg->ctl_rev = SDE_CTL_CFG_VERSION_1_0_0; sde_cfg->delay_prg_fetch_start = true; } else { SDE_ERROR("unsupported chipset id:%X\n", hw_rev); sde_cfg->perf.min_prefill_lines = 0xffff; Loading drivers/gpu/drm/msm/sde/sde_hw_catalog.h +2 −0 Original line number Diff line number Diff line Loading @@ -1027,6 +1027,7 @@ struct sde_perf_cfg { * @ts_prefill_rev prefill traffic shaper feature revision * @macrotile_mode UBWC parameter for macro tile channel distribution * @pipe_order_type indicate if it is required to specify pipe order * @delay_prg_fetch_start indicates if throttling the fetch start is required */ struct sde_mdss_cfg { u32 hwversion; Loading @@ -1053,6 +1054,7 @@ struct sde_mdss_cfg { u32 ts_prefill_rev; u32 macrotile_mode; u32 pipe_order_type; bool delay_prg_fetch_start; bool has_hdr; u32 mdss_count; Loading Loading
drivers/gpu/drm/msm/sde/sde_encoder_phys_vid.c +12 −1 Original line number Diff line number Diff line Loading @@ -216,16 +216,27 @@ static void programmable_fetch_config(struct sde_encoder_phys *phys_enc, u32 vert_total = 0; u32 vfp_fetch_start_vsync_counter = 0; unsigned long lock_flags; struct sde_mdss_cfg *m; if (WARN_ON_ONCE(!phys_enc->hw_intf->ops.setup_prg_fetch)) return; m = phys_enc->sde_kms->catalog; vfp_fetch_lines = programmable_fetch_get_num_lines(vid_enc, timing); if (vfp_fetch_lines) { vert_total = get_vertical_total(timing); horiz_total = get_horizontal_total(timing); vfp_fetch_start_vsync_counter = (vert_total - vfp_fetch_lines) * horiz_total + 1; /** * Check if we need to throttle the fetch to start * from second line after the active region. */ if (m->delay_prg_fetch_start) vfp_fetch_start_vsync_counter += horiz_total; f.enable = 1; f.fetch_start = vfp_fetch_start_vsync_counter; } Loading
drivers/gpu/drm/msm/sde/sde_hw_catalog.c +1 −0 Original line number Diff line number Diff line Loading @@ -3517,6 +3517,7 @@ static int _sde_hardware_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev) sde_cfg->vbif_qos_nlvl = 8; sde_cfg->ts_prefill_rev = 2; sde_cfg->ctl_rev = SDE_CTL_CFG_VERSION_1_0_0; sde_cfg->delay_prg_fetch_start = true; } else { SDE_ERROR("unsupported chipset id:%X\n", hw_rev); sde_cfg->perf.min_prefill_lines = 0xffff; Loading
drivers/gpu/drm/msm/sde/sde_hw_catalog.h +2 −0 Original line number Diff line number Diff line Loading @@ -1027,6 +1027,7 @@ struct sde_perf_cfg { * @ts_prefill_rev prefill traffic shaper feature revision * @macrotile_mode UBWC parameter for macro tile channel distribution * @pipe_order_type indicate if it is required to specify pipe order * @delay_prg_fetch_start indicates if throttling the fetch start is required */ struct sde_mdss_cfg { u32 hwversion; Loading @@ -1053,6 +1054,7 @@ struct sde_mdss_cfg { u32 ts_prefill_rev; u32 macrotile_mode; u32 pipe_order_type; bool delay_prg_fetch_start; bool has_hdr; u32 mdss_count; Loading