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Commit 06547eae authored by Abhijit Kulkarni's avatar Abhijit Kulkarni
Browse files

drm/msm/sde: fix programmable fetch config start 



For sdm855 the display interface was redesigned due to the FIFO
removal in the DSI controller. As a result the DSI controller data
consumption has been decoupled from the timing control.
The data throttling can extend into the next line pushing out the
earliest time programmable fetch can begin. This change effectively
adds another line to the fetch config start position.

Change-Id: I7159d5131d69dd0ef0a424cb03a88f06f14ee3de
Signed-off-by: default avatarAbhijit Kulkarni <kabhijit@codeaurora.org>
parent 90e4b68f

drivers/gpu/drm/msm/sde/sde_encoder_phys_vid.c

+12 −1
Original line number Diff line number Diff line
@@ -216,16 +216,27 @@ static void programmable_fetch_config(struct sde_encoder_phys *phys_enc, 
	u32 vert_total = 0;

	u32 vfp_fetch_start_vsync_counter = 0;

	unsigned long lock_flags;

	struct sde_mdss_cfg *m;



	if (WARN_ON_ONCE(!phys_enc->hw_intf->ops.setup_prg_fetch))

		return;



	m = phys_enc->sde_kms->catalog;



	vfp_fetch_lines = programmable_fetch_get_num_lines(vid_enc, timing);

	if (vfp_fetch_lines) {

		vert_total = get_vertical_total(timing);

		horiz_total = get_horizontal_total(timing);

		vfp_fetch_start_vsync_counter =

			(vert_total - vfp_fetch_lines) * horiz_total + 1;



		/**

		 * Check if we need to throttle the fetch to start

		 * from second line after the active region.

		 */

		if (m->delay_prg_fetch_start)

			vfp_fetch_start_vsync_counter += horiz_total;



		f.enable = 1;

		f.fetch_start = vfp_fetch_start_vsync_counter;

	}

drivers/gpu/drm/msm/sde/sde_hw_catalog.c

+1 −0
Original line number Diff line number Diff line
@@ -3517,6 +3517,7 @@ static int _sde_hardware_caps(struct sde_mdss_cfg *sde_cfg, uint32_t hw_rev) 
		sde_cfg->vbif_qos_nlvl = 8;

		sde_cfg->ts_prefill_rev = 2;

		sde_cfg->ctl_rev = SDE_CTL_CFG_VERSION_1_0_0;

		sde_cfg->delay_prg_fetch_start = true;

	} else {

		SDE_ERROR("unsupported chipset id:%X\n", hw_rev);

		sde_cfg->perf.min_prefill_lines = 0xffff;

drivers/gpu/drm/msm/sde/sde_hw_catalog.h

+2 −0
Original line number Diff line number Diff line
@@ -1027,6 +1027,7 @@ struct sde_perf_cfg { 
 * @ts_prefill_rev     prefill traffic shaper feature revision

 * @macrotile_mode     UBWC parameter for macro tile channel distribution

 * @pipe_order_type    indicate if it is required to specify pipe order

 * @delay_prg_fetch_start indicates if throttling the fetch start is required

 */

struct sde_mdss_cfg {

	u32 hwversion;
@@ -1053,6 +1054,7 @@ struct sde_mdss_cfg { 
	u32 ts_prefill_rev;

	u32 macrotile_mode;

	u32 pipe_order_type;

	bool delay_prg_fetch_start;



	bool has_hdr;

	u32 mdss_count;