Loading arch/arm64/boot/dts/qcom/msm-arm-smmu-qcs405.dtsi +4 −4 Original line number Diff line number Diff line Loading @@ -28,10 +28,10 @@ #size-cells = <1>; #address-cells = <1>; ranges; interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock_gcc GCC_SMMU_CFG_CLK>, <&clock_gcc GCC_GFX_TCU_CLK>; clock-names = "iface_clk", "core_clk"; Loading Loading
arch/arm64/boot/dts/qcom/msm-arm-smmu-qcs405.dtsi +4 −4 Original line number Diff line number Diff line Loading @@ -28,10 +28,10 @@ #size-cells = <1>; #address-cells = <1>; ranges; interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>; clocks = <&clock_gcc GCC_SMMU_CFG_CLK>, <&clock_gcc GCC_GFX_TCU_CLK>; clock-names = "iface_clk", "core_clk"; Loading