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Commit 81436c22 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge changes Ia1946973,Ia974d4e6,I3829114b into msm-4.14 

* changes:
  ARM: dts: msm: Add and enable the clock_gpucc device on SDMSHRIKE
  defconfig: msm: Enable the GPU clock driver for SDMSHRIKE
  clk: qcom: gpucc-sdm855: Add GPU clock driver support for SDMSHRIKE
parents f2ce9375 3a3d8051

Documentation/devicetree/bindings/clock/qcom,gpucc.txt

+3 −2
Original line number Diff line number Diff line
@@ -2,8 +2,9 @@ Qualcomm Technologies, Inc. Graphics Clock & Reset Controller Binding 
--------------------------------------------------------------------



Required properties :

- compatible : shall contain :

		"qcom,gpucc-sdm855"

- compatible : shall contain one of the following:

		"qcom,gpucc-sdm855",

		"qcom,gpucc-sdmshrike".



- reg : shall contain base register offset and size.

- reg-names: names of registers listed in the same order as in the reg property.

arch/arm64/boot/dts/qcom/sdmshrike.dtsi

+11 −0
Original line number Diff line number Diff line
@@ -16,6 +16,7 @@ 
#include <dt-bindings/clock/qcom,npucc-sdm855.h>

#include <dt-bindings/clock/qcom,dispcc-sdm855.h>

#include <dt-bindings/clock/qcom,cpucc-sdm855.h>

#include <dt-bindings/clock/qcom,gpucc-sdm855.h>

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/soc/qcom,tcs-mbox.h>
@@ -518,6 +519,16 @@ 
			"osm_perfcl_base";

		#clock-cells = <1>;

	};



	clock_gpucc: qcom,gpucc@2c90000 {

		compatible = "qcom,gpucc-sdmshrike";

		reg = <0x2c90000 0x9000>;

		reg-names = "cc_base";

		vdd_cx-supply = <&pm855_2_s3_level>;

		vdd_mx-supply = <&pm855p_s3_level>;

		#clock-cells = <1>;

		#reset-cells = <1>;

	};

};



&emac_gdsc {

arch/arm64/configs/sdmshrike-perf_defconfig

+1 −0
Original line number Diff line number Diff line
@@ -300,6 +300,7 @@ CONFIG_MSM_NPUCC_SDM855=y 
CONFIG_CLOCK_CPU_OSM=y

CONFIG_MSM_DISPCC_SDM855=y

CONFIG_MSM_CLK_RPMH=y

CONFIG_MSM_GPUCC_SDM855=y

CONFIG_MSM_GCC_SDMSHRIKE=y

CONFIG_HWSPINLOCK=y

CONFIG_HWSPINLOCK_QCOM=y

arch/arm64/configs/sdmshrike_defconfig

+1 −0
Original line number Diff line number Diff line
@@ -307,6 +307,7 @@ CONFIG_MSM_NPUCC_SDM855=y 
CONFIG_CLOCK_CPU_OSM=y

CONFIG_MSM_DISPCC_SDM855=y

CONFIG_MSM_CLK_RPMH=y

CONFIG_MSM_GPUCC_SDM855=y

CONFIG_MSM_GCC_SDMSHRIKE=y

CONFIG_HWSPINLOCK=y

CONFIG_HWSPINLOCK_QCOM=y

drivers/clk/qcom/Kconfig

+1 −1
Original line number Diff line number Diff line
@@ -292,7 +292,7 @@ config MSM_CLK_RPMH 


config MSM_GPUCC_SDM855

	tristate "SDM855 Graphics Clock Controller"

	depends on MSM_GCC_SDM855

	depends on COMMON_CLK_QCOM

	help

	  Support for the graphics clock controller on Qualcomm Technologies, Inc.

	  sdm855 devices.