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Commit f2ce9375 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add GDSC and dummy clocks support for SDM640" into msm-4.14

parents 3f0df1e3 0926fe9e

arch/arm64/boot/dts/qcom/sdm640-gdsc.dtsi

+5 −5
Original line number Diff line number Diff line
@@ -35,20 +35,20 @@ 
		reg = <0x177004 0x4>;

		qcom,poll-cfg-gdscr;

		status = "disabled";

	;

	};



	usb20_sec_gdsc: qcom,gdsc@1A6004 {

	usb20_sec_gdsc: qcom,gdsc@1a6004 {

		compatible = "regulator-fixed";

		regulator-name = "usb20_sec_gdsc";

		reg = <0x1A6004 0x4>;

		reg = <0x1a6004 0x4>;

		qcom,poll-cfg-gdscr;

		status = "disabled";

	};



	usb30_prim_gdsc: qcom,gdsc@10F004 {

	usb30_prim_gdsc: qcom,gdsc@10f004 {

		compatible = "regulator-fixed";

		regulator-name = "usb30_prim_gdsc";

		reg = <0x10F004 0x4>;

		reg = <0x10f004 0x4>;

		qcom,poll-cfg-gdscr;

		status = "disabled";

	};

arch/arm64/boot/dts/qcom/sdm640.dtsi

+159 −0
Original line number Diff line number Diff line
@@ -12,6 +12,14 @@ 


#include "skeleton64.dtsi"

#include <dt-bindings/interrupt-controller/arm-gic.h>

#include <dt-bindings/clock/qcom,aop-qmp.h>

#include <dt-bindings/clock/qcom,rpmh.h>

#include <dt-bindings/clock/qcom,gcc-sdm640.h>

#include <dt-bindings/clock/qcom,camcc-sdm640.h>

#include <dt-bindings/clock/qcom,cpucc-sdm640.h>

#include <dt-bindings/clock/qcom,dispcc-sdm640.h>

#include <dt-bindings/clock/qcom,gpucc-sdm640.h>

#include <dt-bindings/clock/qcom,videocc-sdm640.h>



/ {

	model = "Qualcomm Technologies, Inc. SDM640";
@@ -400,6 +408,59 @@ 
		};

	};



	clock_rpmh: qcom,rpmhclk {

		compatible = "qcom,dummycc";

		clock-output-names = "rpm_clocks";

		#clock-cells = <1>;

	};



	clock_aop: qcom,aopclk {

		compatible = "qcom,dummycc";

		clock-output-names = "aop_clocks";

		#clock-cells = <1>;

	};



	clock_gcc: qcom,gcc {

		compatible = "qcom,dummycc";

		clock-output-names = "gcc_clocks";

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	clock_videocc: qcom,videocc {

		compatible = "qcom,dummycc";

		clock-output-names = "videocc_clocks";

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	clock_camcc: qcom,camcc {

		compatible = "qcom,dummycc";

		clock-output-names = "camcc_clocks";

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	clock_dispcc: qcom,dispcc {

		compatible = "qcom,dummycc";

		clock-output-names = "dispcc_clocks";

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	clock_gpucc: qcom,gpupcc {

		compatible = "qcom,dummycc";

		clock-output-names = "gpucc_clocks";

		#clock-cells = <1>;

		#reset-cells = <1>;

	};



	clock_cpucc: qcom,cpucc {

		compatible = "qcom,dummycc";

		clock-output-names = "cpucc_clocks";

		#clock-cells = <1>;

	};



	cpu_pmu: cpu-pmu {

		compatible = "arm,armv8-pmuv3";

		qcom,irq-is-percpu;
@@ -610,5 +671,103 @@ 
		};

	};

};



#include "sdm640-pinctrl.dtsi"

#include "sdm640-stub-regulator.dtsi"

#include "sdm640-gdsc.dtsi"



&emac_gdsc {

	status = "ok";

};



&pcie_0_gdsc {

	status = "ok";

};



&ufs_phy_gdsc {

	status = "ok";

};



&usb30_prim_gdsc {

	status = "ok";

};



&usb20_sec_gdsc {

	status = "ok";

};



&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc {

	status = "ok";

};



&hlos1_vote_aggre_noc_mmu_tbu1_gdsc {

	status = "ok";

};



&hlos1_vote_aggre_noc_mmu_tbu2_gdsc {

	status = "ok";

};



&hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc {

	status = "ok";

};



&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc {

	status = "ok";

};



&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc {

	status = "ok";

};



&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc {

	status = "ok";

};



&hlos1_vote_turing_mmu_tbu0_gdsc {

	status = "ok";

};



&hlos1_vote_turing_mmu_tbu1_gdsc {

	status = "ok";

};



&bps_gdsc {

	status = "ok";

};



&ife_0_gdsc {

	status = "ok";

};



&ife_1_gdsc {

	status = "ok";

};



&ipe_0_gdsc {

	status = "ok";

};



&titan_top_gdsc {

	status = "ok";

};



&mdss_core_gdsc {

	status = "ok";

};



&gpu_cx_gdsc {

	status = "ok";

};



&gpu_gx_gdsc {

	status = "ok";

};



&vcodec0_gdsc {

	status = "ok";

};



&venus_gdsc {

	status = "ok";

};

include/dt-bindings/clock/qcom,camcc-sdm640.h

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+122 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SDM640_H

#define _DT_BINDINGS_CLK_QCOM_CAM_CC_SDM640_H



#define CAM_CC_BPS_AHB_CLK					0

#define CAM_CC_BPS_AREG_CLK					1

#define CAM_CC_BPS_AXI_CLK					2

#define CAM_CC_BPS_CLK						3

#define CAM_CC_BPS_CLK_SRC					4

#define CAM_CC_CAMNOC_ATB_CLK					5

#define CAM_CC_CAMNOC_AXI_CLK					6

#define CAM_CC_CCI_CLK						7

#define CAM_CC_CCI_CLK_SRC					8

#define CAM_CC_CORE_AHB_CLK					9

#define CAM_CC_CPAS_AHB_CLK					10

#define CAM_CC_CPHY_RX_CLK_SRC					11

#define CAM_CC_CSI0PHYTIMER_CLK					12

#define CAM_CC_CSI0PHYTIMER_CLK_SRC				13

#define CAM_CC_CSI1PHYTIMER_CLK					14

#define CAM_CC_CSI1PHYTIMER_CLK_SRC				15

#define CAM_CC_CSI2PHYTIMER_CLK					16

#define CAM_CC_CSI2PHYTIMER_CLK_SRC				17

#define CAM_CC_CSIPHY0_CLK					18

#define CAM_CC_CSIPHY1_CLK					19

#define CAM_CC_CSIPHY2_CLK					20

#define CAM_CC_DEBUG_CLK					21

#define CAM_CC_FAST_AHB_CLK_SRC					22

#define CAM_CC_ICP_APB_CLK					23

#define CAM_CC_ICP_ATB_CLK					24

#define CAM_CC_ICP_CLK						25

#define CAM_CC_ICP_CLK_SRC					26

#define CAM_CC_ICP_CTI_CLK					27

#define CAM_CC_ICP_TS_CLK					28

#define CAM_CC_IFE_0_AXI_CLK					29

#define CAM_CC_IFE_0_CLK					30

#define CAM_CC_IFE_0_CLK_SRC					31

#define CAM_CC_IFE_0_CPHY_RX_CLK				32

#define CAM_CC_IFE_0_CSID_CLK					33

#define CAM_CC_IFE_0_CSID_CLK_SRC				34

#define CAM_CC_IFE_0_DSP_CLK					35

#define CAM_CC_IFE_1_AXI_CLK					36

#define CAM_CC_IFE_1_CLK					37

#define CAM_CC_IFE_1_CLK_SRC					38

#define CAM_CC_IFE_1_CPHY_RX_CLK				39

#define CAM_CC_IFE_1_CSID_CLK					40

#define CAM_CC_IFE_1_CSID_CLK_SRC				41

#define CAM_CC_IFE_1_DSP_CLK					42

#define CAM_CC_IFE_LITE_CLK					43

#define CAM_CC_IFE_LITE_CLK_SRC					44

#define CAM_CC_IFE_LITE_CPHY_RX_CLK				45

#define CAM_CC_IFE_LITE_CSID_CLK				46

#define CAM_CC_IFE_LITE_CSID_CLK_SRC				47

#define CAM_CC_IPE_0_AHB_CLK					48

#define CAM_CC_IPE_0_AREG_CLK					49

#define CAM_CC_IPE_0_AXI_CLK					50

#define CAM_CC_IPE_0_CLK					51

#define CAM_CC_IPE_0_CLK_SRC					52

#define CAM_CC_JPEG_CLK						53

#define CAM_CC_JPEG_CLK_SRC					54

#define CAM_CC_LRME_CLK						55

#define CAM_CC_LRME_CLK_SRC					56

#define CAM_CC_MCLK0_CLK					57

#define CAM_CC_MCLK0_CLK_SRC					58

#define CAM_CC_MCLK1_CLK					59

#define CAM_CC_MCLK1_CLK_SRC					60

#define CAM_CC_MCLK2_CLK					61

#define CAM_CC_MCLK2_CLK_SRC					62

#define CAM_CC_MCLK3_CLK					63

#define CAM_CC_MCLK3_CLK_SRC					64

#define CAM_CC_PLL0						65

#define CAM_CC_PLL0_OUT_AUX					66

#define CAM_CC_PLL1						67

#define CAM_CC_PLL1_OUT_AUX					68

#define CAM_CC_PLL2						69

#define CAM_CC_PLL2_OUT_AUX2					70

#define CAM_CC_PLL3						71

#define CAM_CC_PLL3_OUT_MAIN					72

#define CAM_CC_PLL_TEST_CLK					73

#define CAM_CC_SLOW_AHB_CLK_SRC					74

#define CAM_CC_SOC_AHB_CLK					75

#define CAM_CC_SPDM_BPS_CLK					76

#define CAM_CC_SPDM_IFE_0_CLK					77

#define CAM_CC_SPDM_IFE_0_CSID_CLK				78

#define CAM_CC_SPDM_IPE_0_CLK					79

#define CAM_CC_SPDM_JPEG_CLK					80

#define CAM_CC_SYS_TMR_CLK					81



/* TODO: Add PLL Clock IDs */



#define CAM_CC_BPS_BCR						0

#define CAM_CC_CAMNOC_BCR					1

#define CAM_CC_CCI_BCR						2

#define CAM_CC_CPAS_BCR						3

#define CAM_CC_CSI0PHY_BCR					4

#define CAM_CC_CSI1PHY_BCR					5

#define CAM_CC_CSI2PHY_BCR					6

#define CAM_CC_ICP_BCR						7

#define CAM_CC_IFE_0_BCR					8

#define CAM_CC_IFE_1_BCR					9

#define CAM_CC_IFE_LITE_BCR					10

#define CAM_CC_IPE_0_BCR					11

#define CAM_CC_JPEG_BCR						12

#define CAM_CC_LRME_BCR						13

#define CAM_CC_MCLK0_BCR					14

#define CAM_CC_MCLK1_BCR					15

#define CAM_CC_MCLK2_BCR					16

#define CAM_CC_MCLK3_BCR					17

#define CAM_CC_TITAN_TOP_BCR					18



#endif

include/dt-bindings/clock/qcom,cpucc-sdm640.h

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+32 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#ifndef _DT_BINDINGS_CLK_QCOM_CPU_CC_SDM640_H

#define _DT_BINDINGS_CLK_QCOM_CPU_CC_SDM640_H



#define PWRCL_CLK						0

#define PERFCL_CLK						1

#define L3_CLK							2

#define L3_CLUSTER0_VOTE_CLK					3

#define L3_CLUSTER1_VOTE_CLK					4

#define CPU0_PWRCL_CLK						5

#define CPU1_PWRCL_CLK						6

#define CPU2_PWRCL_CLK						7

#define CPU3_PWRCL_CLK						8

#define CPU4_PWRCL_CLK						9

#define CPU5_PWRCL_CLK						10

#define CPU6_PERFCL_CLK						11

#define CPU7_PERFCL_CLK						12

#define L3_MISC_VOTE_CLK					13



#endif

include/dt-bindings/clock/qcom,dispcc-sdm640.h

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+58 −0
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2018, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and

 * only version 2 as published by the Free Software Foundation.

 *

 * This program is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 */



#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_SDM640_H

#define _DT_BINDINGS_CLK_QCOM_DISP_CC_SDM640_H



#define DISP_CC_DEBUG_CLK					0

#define DISP_CC_MDSS_AHB_CLK					1

#define DISP_CC_MDSS_AHB_CLK_SRC				2

#define DISP_CC_MDSS_BYTE0_CLK					3

#define DISP_CC_MDSS_BYTE0_CLK_SRC				4

#define DISP_CC_MDSS_BYTE0_INTF_CLK				5

#define DISP_CC_MDSS_DP_AUX_CLK					6

#define DISP_CC_MDSS_DP_AUX_CLK_SRC				7

#define DISP_CC_MDSS_DP_CRYPTO_CLK				8

#define DISP_CC_MDSS_DP_CRYPTO_CLK_SRC				9

#define DISP_CC_MDSS_DP_LINK_CLK				10

#define DISP_CC_MDSS_DP_LINK_CLK_SRC				11

#define DISP_CC_MDSS_DP_LINK_INTF_CLK				12

#define DISP_CC_MDSS_DP_PIXEL1_CLK				13

#define DISP_CC_MDSS_DP_PIXEL1_CLK_SRC				14

#define DISP_CC_MDSS_DP_PIXEL_CLK				15

#define DISP_CC_MDSS_DP_PIXEL_CLK_SRC				16

#define DISP_CC_MDSS_ESC0_CLK					17

#define DISP_CC_MDSS_ESC0_CLK_SRC				18

#define DISP_CC_MDSS_MDP_CLK					19

#define DISP_CC_MDSS_MDP_CLK_SRC				20

#define DISP_CC_MDSS_MDP_LUT_CLK				21

#define DISP_CC_MDSS_NON_GDSC_AHB_CLK				22

#define DISP_CC_MDSS_PCLK0_CLK					23

#define DISP_CC_MDSS_PCLK0_CLK_SRC				24

#define DISP_CC_MDSS_ROT_CLK					25

#define DISP_CC_MDSS_ROT_CLK_SRC				26

#define DISP_CC_MDSS_RSCC_AHB_CLK				27

#define DISP_CC_MDSS_RSCC_VSYNC_CLK				28

#define DISP_CC_MDSS_VSYNC_CLK					29

#define DISP_CC_MDSS_VSYNC_CLK_SRC				30

#define DISP_CC_PLL0						31

#define DISP_CC_PLL0_OUT_MAIN					32

#define DISP_CC_PLL_TEST_CLK					33

#define DISP_CC_SLEEP_CLK					34

#define DISP_CC_SLEEP_CLK_SRC					35

#define DISP_CC_XO_CLK						36

#define DISP_CC_XO_CLK_SRC					37



#define DISP_CC_MDSS_RSCC_BCR					0



#endif