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Commit 7d167ea7 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Add default pinctrl state for sm8150 HSUART"

parents 7ee9c261 713a7a17

arch/arm64/boot/dts/qcom/sm8150-pinctrl.dtsi

+14 −0
Original line number Diff line number Diff line
@@ -253,6 +253,20 @@ 
		};



		qupv3_se13_4uart_pins: qupv3_se13_4uart_pins {

			qupv3_se13_pins_default: qupv3_se13_pins_default {

				mux {

					pins = "gpio43", "gpio44", "gpio45",

								"gpio46";

					function = "gpio";

					};



				config {

					pins = "gpio43", "gpio44", "gpio45",

								"gpio46";

					drive-strength = <2>;

					bias-disable;

					};

			};

			qupv3_se13_ctsrx: qupv3_se13_ctsrx {

				mux {

					pins = "gpio43", "gpio46";

arch/arm64/boot/dts/qcom/sm8150-qupv3.dtsi

+4 −3
Original line number Diff line number Diff line
@@ -420,11 +420,12 @@ 
		clocks = <&clock_gcc GCC_QUPV3_WRAP2_S3_CLK>,

			<&clock_gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>,

			<&clock_gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>;

		pinctrl-names = "default", "sleep";

		pinctrl-0 = <&qupv3_se13_ctsrx>, <&qupv3_se13_rts>,

						<&qupv3_se13_tx>;

		pinctrl-names = "default", "active", "sleep";

		pinctrl-0 = <&qupv3_se13_pins_default>;

		pinctrl-1 = <&qupv3_se13_ctsrx>, <&qupv3_se13_rts>,

						<&qupv3_se13_tx>;

		pinctrl-2 = <&qupv3_se13_ctsrx>, <&qupv3_se13_rts>,

						<&qupv3_se13_tx>;

		interrupts-extended = <&pdc GIC_SPI 585 0>,

				<&tlmm 46 0>;

		qcom,wrapper-core = <&qupv3_2>;