Merge "ARM: dts: msm: Add initial QUPV3 and Slimbus DT nodes for SDM640" (781e7ebc) · Commits · e / devices / android_kernel_oneplus_sm8150

arch/arm64/boot/dts/qcom/sdm640-pinctrl.dtsi

+375 −0

Original line number	Diff line number	Diff line
		@@ -20,6 +20,8 @@
		interrupt-controller;
		#interrupt-cells = <2>;

		/* QUPv3_0 South SE mappings */
		/* SE 0 pin mappings */
		qupv3_se0_2uart_pins: qupv3_se0_2uart_pins {
		qupv3_se0_2uart_active: qupv3_se0_2uart_active {
		mux {
		@@ -48,6 +50,379 @@
		};
		};

		/* SE 1 pin mappings */
		qupv3_se1_i2c_pins: qupv3_se1_i2c_pins {
		qupv3_se1_i2c_active: qupv3_se1_i2c_active {
		mux {
		pins = "gpio4", "gpio5";
		function = "qup01";
		};

		config {
		pins = "gpio4", "gpio5";
		drive-strength = <2>;
		bias-disable;
		};
		};

		qupv3_se1_i2c_sleep: qupv3_se1_i2c_sleep {
		mux {
		pins = "gpio4", "gpio5";
		function = "gpio";
		};

		config {
		pins = "gpio4", "gpio5";
		drive-strength = <2>;
		bias-pull-up;
		};
		};
		};

		/* SE 2 pin mappings */
		qupv3_se2_i2c_pins: qupv3_se2_i2c_pins {
		qupv3_se2_i2c_active: qupv3_se2_i2c_active {
		mux {
		pins = "gpio0", "gpio1";
		function = "qup02";
		};

		config {
		pins = "gpio0", "gpio1";
		drive-strength = <2>;
		bias-disable;
		};
		};

		qupv3_se2_i2c_sleep: qupv3_se2_i2c_sleep {
		mux {
		pins = "gpio0", "gpio1";
		function = "gpio";
		};

		config {
		pins = "gpio0", "gpio1";
		drive-strength = <2>;
		bias-pull-up;
		};
		};
		};

		qupv3_se2_spi_pins: qupv3_se2_spi_pins {
		qupv3_se2_spi_active: qupv3_se2_spi_active {
		mux {
		pins = "gpio0", "gpio1", "gpio2",
		"gpio3";
		function = "qup02";
		};

		config {
		pins = "gpio0", "gpio1", "gpio2",
		"gpio3";
		drive-strength = <6>;
		bias-disable;
		};
		};

		qupv3_se2_spi_sleep: qupv3_se2_spi_sleep {
		mux {
		pins = "gpio0", "gpio1", "gpio2",
		"gpio3";
		function = "gpio";
		};

		config {
		pins = "gpio0", "gpio1", "gpio2",
		"gpio3";
		drive-strength = <6>;
		bias-disable;
		};
		};
		};

		/* SE 3 pin mappings */
		qupv3_se3_i2c_pins: qupv3_se3_i2c_pins {
		qupv3_se3_i2c_active: qupv3_se3_i2c_active {
		mux {
		pins = "gpio18", "gpio19";
		function = "qup03";
		};

		config {
		pins = "gpio18", "gpio19";
		drive-strength = <2>;
		bias-disable;
		};
		};

		qupv3_se3_i2c_sleep: qupv3_se3_i2c_sleep {
		mux {
		pins = "gpio18", "gpio19";
		function = "gpio";
		};

		config {
		pins = "gpio18", "gpio19";
		drive-strength = <2>;
		bias-pull-up;
		};
		};
		};

		/* QUPv3_1 North instances */
		/* SE 4 pin mappings */
		qupv3_se4_i2c_pins: qupv3_se4_i2c_pins {
		qupv3_se4_i2c_active: qupv3_se4_i2c_active {
		mux {
		pins = "gpio20", "gpio21";
		function = "qup10";
		};

		config {
		pins = "gpio20", "gpio21";
		drive-strength = <2>;
		bias-disable;
		};
		};

		qupv3_se4_i2c_sleep: qupv3_se4_i2c_sleep {
		mux {
		pins = "gpio20", "gpio21";
		function = "gpio";
		};

		config {
		pins = "gpio20", "gpio21";
		drive-strength = <2>;
		bias-pull-up;
		};
		};
		};

		qupv3_se4_spi_pins: qupv3_se4_spi_pins {
		qupv3_se4_spi_active: qupv3_se4_spi_active {
		mux {
		pins = "gpio20", "gpio21", "gpio22",
		"gpio23";
		function = "qup10";
		};

		config {
		pins = "gpio20", "gpio21", "gpio22",
		"gpio23";
		drive-strength = <6>;
		bias-disable;
		};
		};

		qupv3_se4_spi_sleep: qupv3_se4_spi_sleep {
		mux {
		pins = "gpio20", "gpio21", "gpio22",
		"gpio23";
		function = "gpio";
		};

		config {
		pins = "gpio20", "gpio21", "gpio22",
		"gpio23";
		drive-strength = <6>;
		bias-disable;
		};
		};
		};

		/* SE 5 pin mappings */
		qupv3_se5_i2c_pins: qupv3_se5_i2c_pins {
		qupv3_se5_i2c_active: qupv3_se5_i2c_active {
		mux {
		pins = "gpio14", "gpio15";
		function = "qup11";
		};

		config {
		pins = "gpio14", "gpio15";
		drive-strength = <2>;
		bias-disable;
		};
		};

		qupv3_se5_i2c_sleep: qupv3_se5_i2c_sleep {
		mux {
		pins = "gpio14", "gpio15";
		function = "gpio";
		};

		config {
		pins = "gpio14", "gpio15";
		drive-strength = <2>;
		bias-pull-up;
		};
		};
		};

		/* SE 6 pin mappings */
		qupv3_se6_i2c_pins: qupv3_se6_i2c_pins {
		qupv3_se6_i2c_active: qupv3_se6_i2c_active {
		mux {
		pins = "gpio6", "gpio7";
		function = "qup12";
		};

		config {
		pins = "gpio6", "gpio7";
		drive-strength = <2>;
		bias-disable;
		};
		};

		qupv3_se6_i2c_sleep: qupv3_se6_i2c_sleep {
		mux {
		pins = "gpio6", "gpio7";
		function = "gpio";
		};

		config {
		pins = "gpio6", "gpio7";
		drive-strength = <2>;
		bias-pull-up;
		};
		};
		};

		qupv3_se6_spi_pins: qupv3_se6_spi_pins {
		qupv3_se6_spi_active: qupv3_se6_spi_active {
		mux {
		pins = "gpio6", "gpio7", "gpio8",
		"gpio9";
		function = "qup12";
		};

		config {
		pins = "gpio6", "gpio7", "gpio8",
		"gpio9";
		drive-strength = <6>;
		bias-disable;
		};
		};

		qupv3_se6_spi_sleep: qupv3_se6_spi_sleep {
		mux {
		pins = "gpio6", "gpio7", "gpio8",
		"gpio9";
		function = "gpio";
		};

		config {
		pins = "gpio6", "gpio7", "gpio8",
		"gpio9";
		drive-strength = <6>;
		bias-disable;
		};
		};
		};

		/* SE 7 pin mappings */
		qupv3_se7_i2c_pins: qupv3_se7_i2c_pins {
		qupv3_se7_i2c_active: qupv3_se7_i2c_active {
		mux {
		pins = "gpio10", "gpio11";
		function = "qup13";
		};

		config {
		pins = "gpio10", "gpio11";
		drive-strength = <2>;
		bias-disable;
		};
		};

		qupv3_se7_i2c_sleep: qupv3_se7_i2c_sleep {
		mux {
		pins = "gpio10", "gpio11";
		function = "gpio";
		};

		config {
		pins = "gpio10", "gpio11";
		drive-strength = <2>;
		bias-pull-up;
		};
		};
		};

		qupv3_se7_spi_pins: qupv3_se7_spi_pins {
		qupv3_se7_spi_active: qupv3_se7_spi_active {
		mux {
		pins = "gpio10", "gpio11", "gpio12",
		"gpio13";
		function = "qup13";
		};

		config {
		pins = "gpio10", "gpio11", "gpio12",
		"gpio13";
		drive-strength = <6>;
		bias-disable;
		};
		};

		qupv3_se7_spi_sleep: qupv3_se7_spi_sleep {
		mux {
		pins = "gpio10", "gpio11", "gpio12",
		"gpio13";
		function = "gpio";
		};

		config {
		pins = "gpio10", "gpio11", "gpio12",
		"gpio13";
		drive-strength = <6>;
		bias-disable;
		};
		};
		};

		qupv3_se7_4uart_pins: qupv3_se7_4uart_pins {
		qupv3_se7_ctsrx: qupv3_se7_ctsrx {
		mux {
		pins = "gpio10", "gpio13";
		function = "qup13";
		};

		config {
		pins = "gpio10", "gpio13";
		drive-strength = <2>;
		bias-no-pull;
		};
		};

		qupv3_se7_rts: qupv3_se7_rts {
		mux {
		pins = "gpio11";
		function = "qup13";
		};

		config {
		pins = "gpio11";
		drive-strength = <2>;
		bias-pull-down;
		};
		};

		qupv3_se7_tx: qupv3_se7_tx {
		mux {
		pins = "gpio12";
		function = "qup13";
		};

		config {
		pins = "gpio12";
		drive-strength = <2>;
		bias-pull-up;
		};
		};
		};

		/* SDC pin type */
		sdc1_clk_on: sdc1_clk_on {
		config {

arch/arm64/boot/dts/qcom/sdm640-qupv3.dtsi

+289 −1

Original line number	Diff line number	Diff line
		@@ -13,12 +13,30 @@
		#include <dt-bindings/msm/msm-bus-ids.h>

		&soc {
		/* QUPv3 North Instances */
		/*
		* QUPv3 North & South Instances
		* North 0 : SE 4
		* North 1 : SE 5
		* North 2 : SE 6
		* North 3 : SE 7
		* South 0 : SE 0
		* South 1 : SE 1
		* South 2 : SE 2
		* South 3 : SE 3
		*/

		/* QUPv3 South Instances */
		qupv3_0: qcom,qupv3_0_geni_se@8c0000 {
		compatible = "qcom,qupv3-geni-se";
		reg = <0x8c0000 0x6000>;
		qcom,bus-mas-id = <MSM_BUS_MASTER_BLSP_1>;
		qcom,bus-slv-id = <MSM_BUS_SLAVE_EBI_CH0>;
		qcom,iommu-s1-bypass;

		iommu_qupv3_0_geni_se_cb: qcom,iommu_qupv3_0_geni_se_cb {
		compatible = "qcom,qupv3-geni-se-cb";
		iommus = <&apps_smmu 0xc3 0x0>;
		};
		};

		/* Debug UART Instance for CDP/MTP platform */
		@@ -37,4 +55,274 @@
		qcom,wrapper-core = <&qupv3_0>;
		status = "disabled";
		};

		/* I2C */
		qupv3_se1_i2c: i2c@884000 {
		compatible = "qcom,i2c-geni";
		reg = <0x884000 0x4000>;
		interrupts = <GIC_SPI 602 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S1_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		dmas = <&gpi_dma0 0 1 3 64 0>,
		<&gpi_dma0 1 1 3 64 0>;
		dma-names = "tx", "rx";
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se1_i2c_active>;
		pinctrl-1 = <&qupv3_se1_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_0>;
		status = "disabled";
		};

		qupv3_se2_i2c: i2c@888000 {
		compatible = "qcom,i2c-geni";
		reg = <0x888000 0x4000>;
		interrupts = <GIC_SPI 603 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S2_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		dmas = <&gpi_dma0 0 2 3 64 0>,
		<&gpi_dma0 1 2 3 64 0>;
		dma-names = "tx", "rx";
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se2_i2c_active>;
		pinctrl-1 = <&qupv3_se2_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_0>;
		status = "disabled";
		};

		qupv3_se3_i2c: i2c@88c000 {
		compatible = "qcom,i2c-geni";
		reg = <0x88c000 0x4000>;
		interrupts = <GIC_SPI 604 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S3_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		dmas = <&gpi_dma0 0 3 3 64 0>,
		<&gpi_dma0 1 3 3 64 0>;
		dma-names = "tx", "rx";
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se3_i2c_active>;
		pinctrl-1 = <&qupv3_se3_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_0>;
		status = "disabled";
		};

		/* SPI */
		qupv3_se2_spi: spi@888000 {
		compatible = "qcom,spi-geni";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0x888000 0x4000>;
		reg-names = "se_phys";
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP0_S2_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se2_spi_active>;
		pinctrl-1 = <&qupv3_se2_spi_sleep>;
		interrupts = <GIC_SPI 603 0>;
		spi-max-frequency = <50000000>;
		qcom,wrapper-core = <&qupv3_0>;
		dmas = <&gpi_dma0 0 2 1 64 0>,
		<&gpi_dma0 1 2 1 64 0>;
		dma-names = "tx", "rx";
		status = "disabled";
		};

		/* QUPv3 North instances */
		qupv3_1: qcom,qupv3_1_geni_se@ac0000 {
		compatible = "qcom,qupv3-geni-se";
		reg = <0xac0000 0x6000>;
		qcom,bus-mas-id = <MSM_BUS_MASTER_BLSP_2>;
		qcom,bus-slv-id = <MSM_BUS_SLAVE_EBI_CH0>;
		qcom,iommu-s1-bypass;

		iommu_qupv3_1_geni_se_cb: qcom,iommu_qupv3_1_geni_se_cb {
		compatible = "qcom,qupv3-geni-se-cb";
		iommus = <&apps_smmu 0x363 0x0>;
		};
		};

		/* I2C */
		qupv3_se4_i2c: i2c@a80000 {
		compatible = "qcom,i2c-geni";
		reg = <0xa80000 0x4000>;
		interrupts = <GIC_SPI 353 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S0_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		dmas = <&gpi_dma1 0 0 3 64 0>,
		<&gpi_dma1 1 0 3 64 0>;
		dma-names = "tx", "rx";
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se4_i2c_active>;
		pinctrl-1 = <&qupv3_se4_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_1>;
		status = "disabled";
		};

		qupv3_se5_i2c: i2c@a84000 {
		compatible = "qcom,i2c-geni";
		reg = <0xa84000 0x4000>;
		interrupts = <GIC_SPI 354 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S1_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		dmas = <&gpi_dma1 0 1 3 64 0>,
		<&gpi_dma1 1 1 3 64 0>;
		dma-names = "tx", "rx";
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se5_i2c_active>;
		pinctrl-1 = <&qupv3_se5_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_1>;
		status = "disabled";
		};

		qupv3_se6_i2c: i2c@a88000 {
		compatible = "qcom,i2c-geni";
		reg = <0xa88000 0x4000>;
		interrupts = <GIC_SPI 355 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S2_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		dmas = <&gpi_dma1 0 2 3 64 0>,
		<&gpi_dma1 1 2 3 64 0>;
		dma-names = "tx", "rx";
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se6_i2c_active>;
		pinctrl-1 = <&qupv3_se6_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_1>;
		status = "disabled";
		};

		qupv3_se7_i2c: i2c@a8c000 {
		compatible = "qcom,i2c-geni";
		reg = <0xa8c000 0x4000>;
		interrupts = <GIC_SPI 356 0>;
		#address-cells = <1>;
		#size-cells = <0>;
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S3_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		dmas = <&gpi_dma1 0 3 3 64 0>,
		<&gpi_dma1 1 3 3 64 0>;
		dma-names = "tx", "rx";
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se7_i2c_active>;
		pinctrl-1 = <&qupv3_se7_i2c_sleep>;
		qcom,wrapper-core = <&qupv3_1>;
		status = "disabled";
		};

		/* SPI */
		qupv3_se4_spi: spi@a80000 {
		compatible = "qcom,spi-geni";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0xa80000 0x4000>;
		reg-names = "se_phys";
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S0_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se4_spi_active>;
		pinctrl-1 = <&qupv3_se4_spi_sleep>;
		interrupts = <GIC_SPI 353 0>;
		spi-max-frequency = <50000000>;
		qcom,wrapper-core = <&qupv3_1>;
		dmas = <&gpi_dma1 0 0 1 64 0>,
		<&gpi_dma1 1 0 1 64 0>;
		dma-names = "tx", "rx";
		status = "disabled";
		};

		qupv3_se6_spi: spi@a88000 {
		compatible = "qcom,spi-geni";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0xa88000 0x4000>;
		reg-names = "se_phys";
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S2_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se6_spi_active>;
		pinctrl-1 = <&qupv3_se6_spi_sleep>;
		interrupts = <GIC_SPI 355 0>;
		spi-max-frequency = <50000000>;
		qcom,wrapper-core = <&qupv3_1>;
		dmas = <&gpi_dma1 0 2 1 64 0>,
		<&gpi_dma1 1 2 1 64 0>;
		dma-names = "tx", "rx";
		status = "disabled";
		};

		qupv3_se7_spi: spi@a8c000 {
		compatible = "qcom,spi-geni";
		#address-cells = <1>;
		#size-cells = <0>;
		reg = <0xa8c000 0x4000>;
		reg-names = "se_phys";
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S3_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se7_spi_active>;
		pinctrl-1 = <&qupv3_se7_spi_sleep>;
		interrupts = <GIC_SPI 356 0>;
		spi-max-frequency = <50000000>;
		qcom,wrapper-core = <&qupv3_1>;
		dmas = <&gpi_dma1 0 3 1 64 0>,
		<&gpi_dma1 1 3 1 64 0>;
		dma-names = "tx", "rx";
		status = "disabled";
		};

		/*
		* HS UART instances. HS UART usecases can be supported on these
		* instances only.
		*/
		qupv3_se7_4uart: qcom,qup_uart@0xa8c000 {
		compatible = "qcom,msm-geni-serial-hs";
		reg = <0xa8c000 0x4000>;
		reg-names = "se_phys";
		clock-names = "se-clk", "m-ahb", "s-ahb";
		clocks = <&clock_gcc GCC_QUPV3_WRAP1_S3_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>,
		<&clock_gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&qupv3_se7_ctsrx>, <&qupv3_se7_rts>,
		<&qupv3_se7_tx>;
		pinctrl-1 = <&qupv3_se7_ctsrx>, <&qupv3_se7_rts>,
		<&qupv3_se7_tx>;
		interrupts-extended = <&pdc GIC_SPI 356 0>,
		<&tlmm 13 0>;
		status = "disabled";
		qcom,wakeup-byte = <0xFD>;
		qcom,wrapper-core = <&qupv3_1>;
		};
		};

arch/arm64/boot/dts/qcom/sdm640.dtsi

+45 −0

Original line number	Diff line number	Diff line
		@@ -33,6 +33,11 @@
		serial0 = &qupv3_se0_2uart;
		sdhc1 = &sdhc_1; /* SDC1 eMMC slot */
		sdhc2 = &sdhc_2; /* SDC2 SD Card slot */
		spi0 = &qupv3_se4_spi;
		i2c0 = &qupv3_se5_i2c;
		i2c1 = &qupv3_se1_i2c;
		i2c2 = &qupv3_se3_i2c;
		hsuart0 = &qupv3_se7_4uart;
		};

		cpus {
		@@ -999,6 +1004,46 @@
		#interrupt-cells = <4>;
		cell-index = <0>;
		};

		slim_aud: slim@62dc0000 {
		cell-index = <1>;
		compatible = "qcom,slim-ngd";
		reg = <0x62dc0000 0x2c000>,
		<0x62d84000 0x2a000>;
		reg-names = "slimbus_physical", "slimbus_bam_physical";
		interrupts = <0 163 0>, <0 164 0>;
		interrupt-names = "slimbus_irq", "slimbus_bam_irq";
		qcom,apps-ch-pipes = <0x7c0000>;
		qcom,ea-pc = <0x2f0>;
		status = "disabled";
		qcom,iommu-s1-bypass;

		iommu_slim_aud_ctrl_cb: qcom,iommu_slim_ctrl_cb {
		compatible = "qcom,iommu-slim-ctrl-cb";
		iommus = <&apps_smmu 0x17e6 0x0>,
		<&apps_smmu 0x17ed 0x0>,
		<&apps_smmu 0x17ee 0x1>,
		<&apps_smmu 0x17f0 0x1>;
		};

		};

		slim_qca: slim@62e40000 {
		cell-index = <3>;
		compatible = "qcom,slim-ngd";
		reg = <0x62e40000 0x2c000>,
		<0x62e04000 0x20000>;
		reg-names = "slimbus_physical", "slimbus_bam_physical";
		interrupts = <0 291 0>, <0 292 0>;
		interrupt-names = "slimbus_irq", "slimbus_bam_irq";
		status = "disabled";
		qcom,iommu-s1-bypass;

		iommu_slim_qca_ctrl_cb: qcom,iommu_slim_ctrl_cb {
		compatible = "qcom,iommu-slim-ctrl-cb";
		iommus = <&apps_smmu 0x17f3 0x0>;
		};
		};
		};

		#include "pm640.dtsi"