Loading arch/arm64/boot/dts/qcom/trinket-sde.dtsi +5 −3 Original line number Diff line number Diff line Loading @@ -25,16 +25,18 @@ clocks = <&clock_gcc GCC_DISP_AHB_CLK>, <&clock_gcc GCC_DISP_HF_AXI_CLK>, <&clock_gcc GCC_DISP_THROTTLE_CORE_CLK>, <&clock_gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, <&clock_dispcc DISP_CC_MDSS_MDP_CLK>, <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>, <&clock_dispcc DISP_CC_MDSS_MDP_LUT_CLK>, <&clock_dispcc DISP_CC_MDSS_ROT_CLK>; clock-names = "gcc_iface", "gcc_bus", clock-names = "gcc_iface", "gcc_bus", "throttle_clk", "div_clk", "iface_clk", "core_clk", "vsync_clk", "lut_clk", "rot_clk"; clock-rate = <0 0 0 256000000 19200000 192000000>; clock-max-rate = <0 0 0 307000000 19200000 307000000>; clock-rate = <0 0 0 0 0 256000000 19200000 192000000>; clock-max-rate = <0 0 0 0 0 307000000 19200000 307000000>; sde-vdd-supply = <&mdss_core_gdsc>; Loading Loading
arch/arm64/boot/dts/qcom/trinket-sde.dtsi +5 −3 Original line number Diff line number Diff line Loading @@ -25,16 +25,18 @@ clocks = <&clock_gcc GCC_DISP_AHB_CLK>, <&clock_gcc GCC_DISP_HF_AXI_CLK>, <&clock_gcc GCC_DISP_THROTTLE_CORE_CLK>, <&clock_gcc GCC_DISP_GPLL0_DIV_CLK_SRC>, <&clock_dispcc DISP_CC_MDSS_AHB_CLK>, <&clock_dispcc DISP_CC_MDSS_MDP_CLK>, <&clock_dispcc DISP_CC_MDSS_VSYNC_CLK>, <&clock_dispcc DISP_CC_MDSS_MDP_LUT_CLK>, <&clock_dispcc DISP_CC_MDSS_ROT_CLK>; clock-names = "gcc_iface", "gcc_bus", clock-names = "gcc_iface", "gcc_bus", "throttle_clk", "div_clk", "iface_clk", "core_clk", "vsync_clk", "lut_clk", "rot_clk"; clock-rate = <0 0 0 256000000 19200000 192000000>; clock-max-rate = <0 0 0 307000000 19200000 307000000>; clock-rate = <0 0 0 0 0 256000000 19200000 192000000>; clock-max-rate = <0 0 0 0 0 307000000 19200000 307000000>; sde-vdd-supply = <&mdss_core_gdsc>; Loading