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Commit 713aea67 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "ARM: dts: msm: Enable deep pre-fetch for NPU for sm8150"

parents e091af32 d896f9d6

Documentation/devicetree/bindings/iommu/arm,smmu.txt

+8 −0
Original line number Diff line number Diff line
@@ -129,6 +129,14 @@ conditions. 
                  clients who do not detach, it's not possible to keep regulator

                  vote while smmu is attached. Type is <u32>.



- qcom,min-iova-align:

		  Some hardware revision might have the deep prefetch bug where

		  invalid entries in the prefetch window would cause improper

		  permissions to be cached for the valid entries in this window.

		  Enable the workaround on such hardware by aligning the start

		  and end of all mapped buffers to prefetch size boundary, which

		  is defined by ARM_SMMU_MIN_IOVA_ALIGN.



- clocks        : List of clocks to be used during SMMU register access. See

                  Documentation/devicetree/bindings/clock/clock-bindings.txt

                  for information about the format. For each clock specified

arch/arm64/boot/dts/qcom/msm-arm-smmu-sm8150.dtsi

+20 −1
Original line number Diff line number Diff line
@@ -24,6 +24,7 @@ 
		qcom,skip-init;

		qcom,use-3-lvl-tables;

		qcom,disable-atos;

		qcom,min-iova-align;

		#global-interrupts = <1>;

		qcom,regulator-names = "vdd";

		vdd-supply = <&gpu_cx_gdsc>;
@@ -72,6 +73,7 @@ 
		qcom,skip-init;

		qcom,use-3-lvl-tables;

		qcom,disable-atos;

		qcom,min-iova-align;

		#global-interrupts = <1>;

		#size-cells = <1>;

		#address-cells = <1>;
@@ -384,6 +386,23 @@ 
};



&kgsl_smmu {

	qcom,actlr = <0x0 0x407 0x303>;

	qcom,actlr =

		/* All CBs of GFX: +15 deep PF */

		<0x0 0x407 0x303>;

};



&apps_smmu {

	qcom,actlr =

		/* SIDs 0x1460 - 0x1463 of NPU: +3 deep PF */

		<0x1460 0x3 0x103>,



		/* SIDs 0x1464 - 0x1465 of NPU: +3 deep PF */

		<0x1464 0x1 0x103>,



		/* SIDs 0x2060 - 0x2063 of NPU: +3 deep PF */

		<0x2060 0x3 0x103>,



		/* SIDs 0x2064 - 0x2065 of NPU: +3 deep PF */

		<0x2064 0x1 0x103>;

};

drivers/iommu/arm-smmu.c

+5 −2
Original line number Diff line number Diff line
@@ -255,6 +255,7 @@ struct arm_smmu_device { 
#define ARM_SMMU_OPT_NO_ASID_RETENTION	(1 << 5)

#define ARM_SMMU_OPT_STATIC_CB		(1 << 6)

#define ARM_SMMU_OPT_DISABLE_ATOS	(1 << 7)

#define ARM_SMMU_OPT_MIN_IOVA_ALIGN	(1 << 8)

	u32				options;

	enum arm_smmu_arch_version	version;

	enum arm_smmu_implementation	model;
@@ -394,6 +395,7 @@ static struct arm_smmu_option_prop arm_smmu_options[] = { 
	{ ARM_SMMU_OPT_NO_ASID_RETENTION, "qcom,no-asid-retention" },

	{ ARM_SMMU_OPT_STATIC_CB, "qcom,enable-static-cb"},

	{ ARM_SMMU_OPT_DISABLE_ATOS, "qcom,disable-atos" },

	{ ARM_SMMU_OPT_MIN_IOVA_ALIGN, "qcom,min-iova-align" },

	{ 0, NULL},

};
@@ -5344,8 +5346,9 @@ static void qsmmuv500_init_cb(struct arm_smmu_domain *smmu_domain, 
	 * Prefetch only works properly if the start and end of all

	 * buffers in the page table are aligned to ARM_SMMU_MIN_IOVA_ALIGN.

	 */

	if ((iommudata->actlr >> QSMMUV500_ACTLR_DEEP_PREFETCH_SHIFT) &

			QSMMUV500_ACTLR_DEEP_PREFETCH_MASK)

	if (((iommudata->actlr >> QSMMUV500_ACTLR_DEEP_PREFETCH_SHIFT) &

			QSMMUV500_ACTLR_DEEP_PREFETCH_MASK) &&

				  (smmu->options & ARM_SMMU_OPT_MIN_IOVA_ALIGN))

		smmu_domain->qsmmuv500_errata1_min_iova_align = true;

}