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Commit 70f35db1 authored by Package Warehouse Build User's avatar Package Warehouse Build User Committed by Gerrit - the friendly Code Review server
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Merge "drm/msm/sde: add pp1 support for cwb" into dev/msm-4.14-display

parents aafa7e48 79193a57

drivers/gpu/drm/msm/sde/sde_encoder_phys.h

+3 −1
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2015-2018 The Linux Foundation. All rights reserved.

 * Copyright (c) 2015-2019 The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -201,6 +201,7 @@ struct sde_encoder_phys_ops { 
 * @INTR_IDX_UNDERRUN: Underrun unterrupt for video and cmd mode panel

 * @INTR_IDX_RDPTR:    Readpointer done unterrupt for cmd mode panel

 * @INTR_IDX_WB_DONE:  Writeback done interrupt for WB

 * @INTR_IDX_PP1_OVFL: Pingpong overflow interrupt on PP1 for Concurrent WB

 * @INTR_IDX_PP2_OVFL: Pingpong overflow interrupt on PP2 for Concurrent WB

 * @INTR_IDX_PP3_OVFL: Pingpong overflow interrupt on PP3 for Concurrent WB

 * @INTR_IDX_PP4_OVFL: Pingpong overflow interrupt on PP4 for Concurrent WB
@@ -216,6 +217,7 @@ enum sde_intr_idx { 
	INTR_IDX_RDPTR,

	INTR_IDX_AUTOREFRESH_DONE,

	INTR_IDX_WB_DONE,

	INTR_IDX_PP1_OVFL,

	INTR_IDX_PP2_OVFL,

	INTR_IDX_PP3_OVFL,

	INTR_IDX_PP4_OVFL,

drivers/gpu/drm/msm/sde/sde_encoder_phys_wb.c

+12 −2
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2015-2018 The Linux Foundation. All rights reserved.

 * Copyright (c) 2015-2019 The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -32,7 +32,7 @@ 


#define TO_S15D16(_x_)	((_x_) << 7)



static const u32 cwb_irq_tbl[PINGPONG_MAX] = {SDE_NONE, SDE_NONE,

static const u32 cwb_irq_tbl[PINGPONG_MAX] = {SDE_NONE, INTR_IDX_PP1_OVFL,

	INTR_IDX_PP2_OVFL, INTR_IDX_PP3_OVFL, INTR_IDX_PP4_OVFL,

	INTR_IDX_PP5_OVFL, SDE_NONE, SDE_NONE};
@@ -1811,6 +1811,16 @@ struct sde_encoder_phys *sde_encoder_phys_wb_init( 
	irq->cb.arg = wb_enc;

	irq->cb.func = sde_encoder_phys_wb_done_irq;



	irq = &phys_enc->irq[INTR_IDX_PP1_OVFL];

	INIT_LIST_HEAD(&irq->cb.list);

	irq->name = "pp1_overflow";

	irq->hw_idx = CWB_1;

	irq->irq_idx = -1;

	irq->intr_type = SDE_IRQ_TYPE_CWB_OVERFLOW;

	irq->intr_idx = INTR_IDX_PP1_OVFL;

	irq->cb.arg = wb_enc;

	irq->cb.func = sde_encoder_phys_cwb_ovflow;



	irq = &phys_enc->irq[INTR_IDX_PP2_OVFL];

	INIT_LIST_HEAD(&irq->cb.list);

	irq->name = "pp2_overflow";

drivers/gpu/drm/msm/sde/sde_hw_ctl.c

+3 −3
Original line number Diff line number Diff line 
/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.

/* Copyright (c) 2015-2019, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -143,7 +143,7 @@ static const u32 cdm_flush_tbl[CDM_MAX] = {SDE_NONE, 0}; 
/**

 * list of CWB bits in CTL_CWB_FLUSH

 */

static const u32 cwb_flush_tbl[CWB_MAX] = {SDE_NONE, SDE_NONE, SDE_NONE, 2, 3,

static const u32 cwb_flush_tbl[CWB_MAX] = {SDE_NONE, SDE_NONE, 1, 2, 3,

	4, 5};



/**
@@ -576,7 +576,7 @@ static inline int sde_hw_ctl_update_bitmask_cwb_v1(struct sde_hw_ctl *ctx, 
	if (!ctx)

		return -EINVAL;



	if ((cwb < CWB_2) || (cwb >= CWB_MAX)) {

	if ((cwb < CWB_1) || (cwb >= CWB_MAX)) {

		SDE_ERROR("Unsupported cwb %d\n", cwb);

		return -EINVAL;

	}

drivers/gpu/drm/msm/sde/sde_hw_interrupts.c

+5 −3
Original line number Diff line number Diff line 
/* Copyright (c) 2016-2018, The Linux Foundation. All rights reserved.

/* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -128,6 +128,7 @@ 
/**

 * Concurrent WB overflow interrupt status bit definitions

 */

#define SDE_INTR_CWB_1_OVERFLOW BIT(8)

#define SDE_INTR_CWB_2_OVERFLOW BIT(14)

#define SDE_INTR_CWB_3_OVERFLOW BIT(15)

#define SDE_INTR_CWB_4_OVERFLOW BIT(20)
@@ -358,12 +359,13 @@ static const struct sde_irq_type sde_irq_map[] = { 
	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 1},

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 1},

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 1},

	/* irq_idx: 36-39 */

	/* irq_idx: 36-38 */

	{ SDE_IRQ_TYPE_PING_PONG_WR_PTR, PINGPONG_S0,

		SDE_INTR_PING_PONG_S0_WR_PTR, 1},

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 1},

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 1},

	{ SDE_IRQ_TYPE_RESERVED, 0, 0, 1},

	/* irq_idx: 39 */

	{ SDE_IRQ_TYPE_CWB_OVERFLOW, CWB_1, SDE_INTR_CWB_1_OVERFLOW, 1},

	/* irq_idx: 40 */

	{ SDE_IRQ_TYPE_PING_PONG_RD_PTR, PINGPONG_S0,

		SDE_INTR_PING_PONG_S0_RD_PTR, 1},