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Commit 67737244 authored by Ray Zhang's avatar Ray Zhang Committed by Yujun Zhang
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msm: clk: qcom: power on PLL when reading PLL registers 



On sm8150 platform, reading register of DSI PLL would
fail if PLL is not powered up, so enable DSI PLL power
before reading operation.

CRs-Fixed: 2225631
Change-Id: I2d589ee39b95234b06c8ad6556725f94deea2c10
Signed-off-by: default avatarRay Zhang <rayz@codeaurora.org>
Signed-off-by: default avatarYujun Zhang <yujunzhang@codeaurora.org>
parent 150e5aba

drivers/clk/qcom/mdss/mdss-dsi-pll-7nm.c

+13 −0
Original line number Diff line number Diff line
@@ -254,6 +254,7 @@ static inline int pll_reg_read(void *context, unsigned int reg, 
					unsigned int *val)

{

	int rc = 0;

	u32 data;

	struct mdss_pll_resources *rsc = context;



	rc = mdss_pll_resource_enable(rsc, true);
@@ -262,7 +263,19 @@ static inline int pll_reg_read(void *context, unsigned int reg, 
		return rc;

	}



	/*

	 * DSI PHY/PLL should be both powered on when reading PLL

	 * registers. Since PHY power has been enabled in DSI PHY

	 * driver, only PLL power is needed to enable here.

	 */

	data = MDSS_PLL_REG_R(rsc->phy_base, PHY_CMN_CTRL_0);

	MDSS_PLL_REG_W(rsc->phy_base, PHY_CMN_CTRL_0, data | BIT(5));

	ndelay(250);



	*val = MDSS_PLL_REG_R(rsc->pll_base, reg);



	MDSS_PLL_REG_W(rsc->phy_base, PHY_CMN_CTRL_0, data);



	(void)mdss_pll_resource_enable(rsc, false);



	return rc;