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Commit 62d9a00e authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
Browse files

Merge "clk: qcom: Assign pll config to video/disp/camcc/gpu/ssc pll"

parents 98b3af66 dc0293e9

drivers/clk/qcom/camcc-sm8150.c

+25 −23
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.

 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -163,7 +163,7 @@ static struct pll_vco trion_vco[] = { 
	{ 249600000, 2000000000, 0 },

};



static const struct alpha_pll_config cam_cc_pll0_config = {

static struct alpha_pll_config cam_cc_pll0_config = {

	.l = 0x3E,

	.alpha = 0x8000,

	.config_ctl_val = 0x20485699,
@@ -177,7 +177,7 @@ static const struct alpha_pll_config cam_cc_pll0_config = { 
	.user_ctl_hi1_val = 0x000000D0,

};



static const struct alpha_pll_config cam_cc_pll0_config_sm8150_v2 = {

static struct alpha_pll_config cam_cc_pll0_config_sm8150_v2 = {

	.l = 0x3E,

	.alpha = 0x8000,

	.config_ctl_val = 0x20485699,
@@ -196,6 +196,7 @@ static struct clk_alpha_pll cam_cc_pll0 = { 
	.vco_table = trion_vco,

	.num_vco = ARRAY_SIZE(trion_vco),

	.type = TRION_PLL,

	.config = &cam_cc_pll0_config,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "cam_cc_pll0",
@@ -253,7 +254,7 @@ static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = { 
	},

};



static const struct alpha_pll_config cam_cc_pll1_config = {

static struct alpha_pll_config cam_cc_pll1_config = {

	.l = 0x1F,

	.alpha = 0x4000,

	.config_ctl_val = 0x20485699,
@@ -267,7 +268,7 @@ static const struct alpha_pll_config cam_cc_pll1_config = { 
	.user_ctl_hi1_val = 0x000000D0,

};



static const struct alpha_pll_config cam_cc_pll1_config_sm8150_v2 = {

static struct alpha_pll_config cam_cc_pll1_config_sm8150_v2 = {

	.l = 0x1F,

	.alpha = 0x4000,

	.config_ctl_val = 0x20485699,
@@ -286,6 +287,7 @@ static struct clk_alpha_pll cam_cc_pll1 = { 
	.vco_table = trion_vco,

	.num_vco = ARRAY_SIZE(trion_vco),

	.type = TRION_PLL,

	.config = &cam_cc_pll1_config,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "cam_cc_pll1",
@@ -318,7 +320,7 @@ static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = { 
	},

};



static const struct alpha_pll_config cam_cc_pll2_config = {

static struct alpha_pll_config cam_cc_pll2_config = {

	.l = 0x32,

	.alpha = 0x0,

	.config_ctl_val = 0x10000807,
@@ -335,6 +337,7 @@ static struct clk_alpha_pll cam_cc_pll2 = { 
	.vco_table = regera_vco,

	.num_vco = ARRAY_SIZE(regera_vco),

	.type = REGERA_PLL,

	.config = &cam_cc_pll2_config,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "cam_cc_pll2",
@@ -373,7 +376,7 @@ static struct clk_alpha_pll_postdiv cam_cc_pll2_out_main = { 
	},

};



static const struct alpha_pll_config cam_cc_pll3_config = {

static struct alpha_pll_config cam_cc_pll3_config = {

	.l = 0x29,

	.alpha = 0xAAAA,

	.config_ctl_val = 0x20485699,
@@ -387,7 +390,7 @@ static const struct alpha_pll_config cam_cc_pll3_config = { 
	.user_ctl_hi1_val = 0x000000D0,

};



static const struct alpha_pll_config cam_cc_pll3_config_sm8150_v2 = {

static struct alpha_pll_config cam_cc_pll3_config_sm8150_v2 = {

	.l = 0x29,

	.alpha = 0xAAAA,

	.config_ctl_val = 0x20485699,
@@ -406,6 +409,7 @@ static struct clk_alpha_pll cam_cc_pll3 = { 
	.vco_table = trion_vco,

	.num_vco = ARRAY_SIZE(trion_vco),

	.type = TRION_PLL,

	.config = &cam_cc_pll3_config,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "cam_cc_pll3",
@@ -438,7 +442,7 @@ static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = { 
	},

};



static const struct alpha_pll_config cam_cc_pll4_config = {

static struct alpha_pll_config cam_cc_pll4_config = {

	.l = 0x29,

	.alpha = 0xAAAA,

	.config_ctl_val = 0x20485699,
@@ -452,7 +456,7 @@ static const struct alpha_pll_config cam_cc_pll4_config = { 
	.user_ctl_hi1_val = 0x000000D0,

};



static const struct alpha_pll_config cam_cc_pll4_config_sm8150_v2 = {

static struct alpha_pll_config cam_cc_pll4_config_sm8150_v2 = {

	.l = 0x29,

	.alpha = 0xAAAA,

	.config_ctl_val = 0x20485699,
@@ -471,6 +475,7 @@ static struct clk_alpha_pll cam_cc_pll4 = { 
	.vco_table = trion_vco,

	.num_vco = ARRAY_SIZE(trion_vco),

	.type = TRION_PLL,

	.config = &cam_cc_pll4_config,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "cam_cc_pll4",
@@ -2421,14 +2426,11 @@ MODULE_DEVICE_TABLE(of, cam_cc_sm8150_match_table); 


static void cam_cc_sm8150_fixup_sm8150v2(struct regmap *regmap)

{

	clk_trion_pll_configure(&cam_cc_pll0, regmap,

		&cam_cc_pll0_config_sm8150_v2);

	clk_trion_pll_configure(&cam_cc_pll1, regmap,

		&cam_cc_pll1_config_sm8150_v2);

	clk_trion_pll_configure(&cam_cc_pll3, regmap,

		&cam_cc_pll3_config_sm8150_v2);

	clk_trion_pll_configure(&cam_cc_pll4, regmap,

		&cam_cc_pll4_config_sm8150_v2);

	cam_cc_pll0.config = &cam_cc_pll0_config_sm8150_v2;

	cam_cc_pll1.config = &cam_cc_pll1_config_sm8150_v2;

	cam_cc_pll3.config = &cam_cc_pll3_config_sm8150_v2;

	cam_cc_pll4.config = &cam_cc_pll4_config_sm8150_v2;



	cam_cc_ife_0_clk_src.freq_tbl = ftbl_cam_cc_ife_0_clk_src_sm8150_v2;

	cam_cc_ife_0_clk_src.clkr.hw.init->rate_max[VDD_NOMINAL] = 847000000;

	cam_cc_ife_0_clk_src.clkr.hw.init->rate_max[VDD_HIGH] = 950000000;
@@ -2510,11 +2512,11 @@ static int cam_cc_sm8150_probe(struct platform_device *pdev) 
	if (ret)

		return ret;



	clk_trion_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config);

	clk_trion_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config);

	clk_regera_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config);

	clk_trion_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config);

	clk_trion_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config);

	clk_trion_pll_configure(&cam_cc_pll0, regmap, cam_cc_pll0.config);

	clk_trion_pll_configure(&cam_cc_pll1, regmap, cam_cc_pll1.config);

	clk_regera_pll_configure(&cam_cc_pll2, regmap, cam_cc_pll2.config);

	clk_trion_pll_configure(&cam_cc_pll3, regmap, cam_cc_pll3.config);

	clk_trion_pll_configure(&cam_cc_pll4, regmap, cam_cc_pll4.config);



	ret = qcom_cc_really_probe(pdev, &cam_cc_sm8150_desc, regmap);

	if (ret) {

drivers/clk/qcom/clk-alpha-pll.c

+35 −2
Original line number Diff line number Diff line
@@ -781,6 +781,11 @@ int clk_trion_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 
{

	int ret = 0;



	if (!config) {

		pr_err("PLL configuration missing.\n");

		return -EINVAL;

	}



	if (pll->inited)

		return ret;
@@ -867,7 +872,7 @@ static int clk_trion_pll_enable(struct clk_hw *hw) 
{

	int ret;

	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);

	u32 val, off = pll->offset;

	u32 val, off = pll->offset, l_val, cal_val;



	ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val);

	if (ret)
@@ -881,6 +886,19 @@ static int clk_trion_pll_enable(struct clk_hw *hw) 
		return wait_for_pll_enable_active(pll);

	}



	ret = regmap_read(pll->clkr.regmap, pll->offset + PLL_L_VAL, &l_val);

	if (ret)

		return ret;



	ret = regmap_read(pll->clkr.regmap, pll->offset + TRION_PLL_CAL_L_VAL,

				&cal_val);

	if (ret)

		return ret;



	/* PLL has lost it's L or CAL value, needs reconfiguration */

	if (!l_val || !cal_val)

		pll->inited = false;



	if (unlikely(!pll->inited)) {

		ret = clk_trion_pll_configure(pll, pll->clkr.regmap,

						pll->config);
@@ -888,6 +906,7 @@ static int clk_trion_pll_enable(struct clk_hw *hw) 
			pr_err("Failed to configure %s\n", clk_hw_get_name(hw));

			return ret;

		}

		pr_warn("PLL configuration lost, reconfiguration of PLL done.\n");

	}



	/* Set operation mode to RUN */
@@ -1083,6 +1102,11 @@ int clk_regera_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap, 
	u32 mode_regval;

	int ret = 0;



	if (!config) {

		pr_err("PLL configuration missing.\n");

		return -EINVAL;

	}



	if (pll->inited)

		return ret;
@@ -1145,7 +1169,7 @@ static int clk_regera_pll_enable(struct clk_hw *hw) 
{

	int ret;

	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);

	u32 val, off = pll->offset;

	u32 val, off = pll->offset, l_val;



	ret = regmap_read(pll->clkr.regmap, off + PLL_MODE, &val);

	if (ret)
@@ -1159,6 +1183,14 @@ static int clk_regera_pll_enable(struct clk_hw *hw) 
		return wait_for_pll_enable_active(pll);

	}



	ret = regmap_read(pll->clkr.regmap, off + PLL_L_VAL, &l_val);

	if (ret)

		return ret;



	/* PLL has lost it's L value, needs reconfiguration */

	if (!l_val)

		pll->inited = false;



	if (unlikely(!pll->inited)) {

		ret = clk_regera_pll_configure(pll, pll->clkr.regmap,

						pll->config);
@@ -1166,6 +1198,7 @@ static int clk_regera_pll_enable(struct clk_hw *hw) 
			pr_err("Failed to configure %s\n", clk_hw_get_name(hw));

			return ret;

		}

		pr_warn("PLL configuration lost, reconfiguration of PLL done.\n");

	}



	/* Get the PLL out of bypass mode */

drivers/clk/qcom/dispcc-sm8150.c

+11 −10
Original line number Diff line number Diff line
@@ -204,7 +204,7 @@ static struct pll_vco trion_vco[] = { 
	{ 249600000, 2000000000, 0 },

};



static const struct alpha_pll_config disp_cc_pll0_config = {

static struct alpha_pll_config disp_cc_pll0_config = {

	.l = 0x47,

	.alpha = 0xE000,

	.config_ctl_val = 0x20485699,
@@ -218,7 +218,7 @@ static const struct alpha_pll_config disp_cc_pll0_config = { 
	.user_ctl_hi1_val = 0x000000D0,

};



static const struct alpha_pll_config disp_cc_pll0_config_sm8150_v2 = {

static struct alpha_pll_config disp_cc_pll0_config_sm8150_v2 = {

	.l = 0x47,

	.alpha = 0xE000,

	.config_ctl_val = 0x20485699,
@@ -234,6 +234,7 @@ static struct clk_alpha_pll disp_cc_pll0 = { 
	.vco_table = trion_vco,

	.num_vco = ARRAY_SIZE(trion_vco),

	.type = TRION_PLL,

	.config = &disp_cc_pll0_config,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "disp_cc_pll0",
@@ -251,7 +252,7 @@ static struct clk_alpha_pll disp_cc_pll0 = { 
	},

};



static const struct alpha_pll_config disp_cc_pll1_config = {

static struct alpha_pll_config disp_cc_pll1_config = {

	.l = 0x1F,

	.alpha = 0x4000,

	.config_ctl_val = 0x20485699,
@@ -265,7 +266,7 @@ static const struct alpha_pll_config disp_cc_pll1_config = { 
	.user_ctl_hi1_val = 0x000000D0,

};



static const struct alpha_pll_config disp_cc_pll1_config_sm8150_v2 = {

static struct alpha_pll_config disp_cc_pll1_config_sm8150_v2 = {

	.l = 0x1F,

	.alpha = 0x4000,

	.config_ctl_val = 0x20485699,
@@ -281,6 +282,7 @@ static struct clk_alpha_pll disp_cc_pll1 = { 
	.vco_table = trion_vco,

	.num_vco = ARRAY_SIZE(trion_vco),

	.type = TRION_PLL,

	.config = &disp_cc_pll1_config,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "disp_cc_pll1",
@@ -1553,10 +1555,9 @@ MODULE_DEVICE_TABLE(of, disp_cc_sm8150_match_table); 


static void disp_cc_sm8150_fixup_sm8150v2(struct regmap *regmap)

{

	clk_trion_pll_configure(&disp_cc_pll0, regmap,

		&disp_cc_pll0_config_sm8150_v2);

	clk_trion_pll_configure(&disp_cc_pll1, regmap,

		&disp_cc_pll1_config_sm8150_v2);

	disp_cc_pll0.config = &disp_cc_pll0_config_sm8150_v2;

	disp_cc_pll1.config = &disp_cc_pll1_config_sm8150_v2;



	disp_cc_mdss_dp_pixel1_clk_src.clkr.hw.init->rate_max[VDD_LOW_L1] =

		337500;

	disp_cc_mdss_dp_pixel1_clk_src.clkr.hw.init->rate_max[VDD_NOMINAL] =
@@ -1653,8 +1654,8 @@ static int disp_cc_sm8150_probe(struct platform_device *pdev) 
	if (ret)

		return ret;



	clk_trion_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);

	clk_trion_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);

	clk_trion_pll_configure(&disp_cc_pll0, regmap, disp_cc_pll0.config);

	clk_trion_pll_configure(&disp_cc_pll1, regmap, disp_cc_pll1.config);



	/* Enable clock gating for DSI and MDP clocks */

	regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10);

drivers/clk/qcom/gpucc-sm8150.c

+5 −4
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2018, The Linux Foundation. All rights reserved.

 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -72,7 +72,7 @@ static struct pll_vco trion_vco[] = { 
	{ 249600000, 2000000000, 0 },

};



static const struct alpha_pll_config gpu_cc_pll1_config = {

static struct alpha_pll_config gpu_cc_pll1_config = {

	.l = 0x1A,

	.alpha = 0xAAA,

	.config_ctl_val = 0x20485699,
@@ -90,6 +90,7 @@ static struct clk_alpha_pll gpu_cc_pll1 = { 
	.offset = 0x100,

	.vco_table = trion_vco,

	.num_vco = ARRAY_SIZE(trion_vco),

	.config = &gpu_cc_pll1_config,

	.type = TRION_PLL,

	.clkr = {

		.hw.init = &(struct clk_init_data){
@@ -484,8 +485,6 @@ static int gpu_cc_sm8150_probe(struct platform_device *pdev) 
		return PTR_ERR(vdd_mx.regulator[0]);

	}



	clk_trion_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);



	gpu_cc_sm8150_fixup(pdev);



	for (i = 0; i < ARRAY_SIZE(gpu_cc_sm8150_hws); i++) {
@@ -494,6 +493,8 @@ static int gpu_cc_sm8150_probe(struct platform_device *pdev) 
			return PTR_ERR(clk);

	}



	clk_trion_pll_configure(&gpu_cc_pll1, regmap, gpu_cc_pll1.config);



	ret = qcom_cc_really_probe(pdev, &gpu_cc_sm8150_desc, regmap);

	if (ret) {

		dev_err(&pdev->dev, "Failed to register GPU CC clocks\n");

drivers/clk/qcom/scc-sm8150.c

+7 −5
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2018, The Linux Foundation. All rights reserved.

 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -75,7 +75,7 @@ static struct pll_vco trion_vco[] = { 
	{ 249600000, 2000000000, 0 },

};



static const struct alpha_pll_config scc_pll_config = {

static struct alpha_pll_config scc_pll_config = {

	.l = 0x1F,

	.alpha = 0x4000,

	.config_ctl_val = 0x20485699,
@@ -89,7 +89,7 @@ static const struct alpha_pll_config scc_pll_config = { 
	.user_ctl_hi1_val = 0x000000D0,

};



static const struct alpha_pll_config scc_pll_config_sm8150_v2 = {

static struct alpha_pll_config scc_pll_config_sm8150_v2 = {

	.l = 0x1E,

	.alpha = 0x0,

	.config_ctl_val = 0x20485699,
@@ -105,6 +105,7 @@ static struct clk_alpha_pll scc_pll = { 
	.vco_table = trion_vco,

	.num_vco = ARRAY_SIZE(trion_vco),

	.type = TRION_PLL,

	.config = &scc_pll_config,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "scc_pll",
@@ -581,7 +582,8 @@ MODULE_DEVICE_TABLE(of, scc_sm8150_match_table); 


static void scc_sm8150_fixup_sm8150v2(struct regmap *regmap)

{

	clk_trion_pll_configure(&scc_pll, regmap, &scc_pll_config_sm8150_v2);

	scc_pll.config = &scc_pll_config_sm8150_v2;



	scc_main_rcg_clk_src.freq_tbl = ftbl_scc_main_rcg_clk_src_sm8150_v2;

	scc_main_rcg_clk_src.clkr.hw.init->rate_max[VDD_MIN] = 96000000;

	scc_main_rcg_clk_src.clkr.hw.init->rate_max[VDD_LOW] = 576000000;
@@ -663,7 +665,7 @@ static int scc_sm8150_probe(struct platform_device *pdev) 
	if (ret)

		return ret;



	clk_trion_pll_configure(&scc_pll, regmap, &scc_pll_config);

	clk_trion_pll_configure(&scc_pll, regmap, scc_pll.config);



	ret = qcom_cc_really_probe(pdev, &scc_sm8150_desc, regmap);

	if (ret) {