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Commit dc0293e9 authored by Taniya Das's avatar Taniya Das
Browse files

clk: qcom: Assign pll config to video/disp/camcc/gpu/ssc pll 



Add the PLL configs for all the clock controller PLLs to allow
reconfiguration in the case the configurations are lost.

Change-Id: I5d049b763254f35847614de6e099dd4f8575b0b9
Signed-off-by: default avatarTaniya Das <tdas@codeaurora.org>
parent 8cdf021a

drivers/clk/qcom/camcc-sm8150.c

+25 −23
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.

 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -163,7 +163,7 @@ static struct pll_vco trion_vco[] = { 
	{ 249600000, 2000000000, 0 },

};



static const struct alpha_pll_config cam_cc_pll0_config = {

static struct alpha_pll_config cam_cc_pll0_config = {

	.l = 0x3E,

	.alpha = 0x8000,

	.config_ctl_val = 0x20485699,
@@ -177,7 +177,7 @@ static const struct alpha_pll_config cam_cc_pll0_config = { 
	.user_ctl_hi1_val = 0x000000D0,

};



static const struct alpha_pll_config cam_cc_pll0_config_sm8150_v2 = {

static struct alpha_pll_config cam_cc_pll0_config_sm8150_v2 = {

	.l = 0x3E,

	.alpha = 0x8000,

	.config_ctl_val = 0x20485699,
@@ -196,6 +196,7 @@ static struct clk_alpha_pll cam_cc_pll0 = { 
	.vco_table = trion_vco,

	.num_vco = ARRAY_SIZE(trion_vco),

	.type = TRION_PLL,

	.config = &cam_cc_pll0_config,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "cam_cc_pll0",
@@ -253,7 +254,7 @@ static struct clk_alpha_pll_postdiv cam_cc_pll0_out_odd = { 
	},

};



static const struct alpha_pll_config cam_cc_pll1_config = {

static struct alpha_pll_config cam_cc_pll1_config = {

	.l = 0x1F,

	.alpha = 0x4000,

	.config_ctl_val = 0x20485699,
@@ -267,7 +268,7 @@ static const struct alpha_pll_config cam_cc_pll1_config = { 
	.user_ctl_hi1_val = 0x000000D0,

};



static const struct alpha_pll_config cam_cc_pll1_config_sm8150_v2 = {

static struct alpha_pll_config cam_cc_pll1_config_sm8150_v2 = {

	.l = 0x1F,

	.alpha = 0x4000,

	.config_ctl_val = 0x20485699,
@@ -286,6 +287,7 @@ static struct clk_alpha_pll cam_cc_pll1 = { 
	.vco_table = trion_vco,

	.num_vco = ARRAY_SIZE(trion_vco),

	.type = TRION_PLL,

	.config = &cam_cc_pll1_config,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "cam_cc_pll1",
@@ -318,7 +320,7 @@ static struct clk_alpha_pll_postdiv cam_cc_pll1_out_even = { 
	},

};



static const struct alpha_pll_config cam_cc_pll2_config = {

static struct alpha_pll_config cam_cc_pll2_config = {

	.l = 0x32,

	.alpha = 0x0,

	.config_ctl_val = 0x10000807,
@@ -335,6 +337,7 @@ static struct clk_alpha_pll cam_cc_pll2 = { 
	.vco_table = regera_vco,

	.num_vco = ARRAY_SIZE(regera_vco),

	.type = REGERA_PLL,

	.config = &cam_cc_pll2_config,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "cam_cc_pll2",
@@ -373,7 +376,7 @@ static struct clk_alpha_pll_postdiv cam_cc_pll2_out_main = { 
	},

};



static const struct alpha_pll_config cam_cc_pll3_config = {

static struct alpha_pll_config cam_cc_pll3_config = {

	.l = 0x29,

	.alpha = 0xAAAA,

	.config_ctl_val = 0x20485699,
@@ -387,7 +390,7 @@ static const struct alpha_pll_config cam_cc_pll3_config = { 
	.user_ctl_hi1_val = 0x000000D0,

};



static const struct alpha_pll_config cam_cc_pll3_config_sm8150_v2 = {

static struct alpha_pll_config cam_cc_pll3_config_sm8150_v2 = {

	.l = 0x29,

	.alpha = 0xAAAA,

	.config_ctl_val = 0x20485699,
@@ -406,6 +409,7 @@ static struct clk_alpha_pll cam_cc_pll3 = { 
	.vco_table = trion_vco,

	.num_vco = ARRAY_SIZE(trion_vco),

	.type = TRION_PLL,

	.config = &cam_cc_pll3_config,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "cam_cc_pll3",
@@ -438,7 +442,7 @@ static struct clk_alpha_pll_postdiv cam_cc_pll3_out_even = { 
	},

};



static const struct alpha_pll_config cam_cc_pll4_config = {

static struct alpha_pll_config cam_cc_pll4_config = {

	.l = 0x29,

	.alpha = 0xAAAA,

	.config_ctl_val = 0x20485699,
@@ -452,7 +456,7 @@ static const struct alpha_pll_config cam_cc_pll4_config = { 
	.user_ctl_hi1_val = 0x000000D0,

};



static const struct alpha_pll_config cam_cc_pll4_config_sm8150_v2 = {

static struct alpha_pll_config cam_cc_pll4_config_sm8150_v2 = {

	.l = 0x29,

	.alpha = 0xAAAA,

	.config_ctl_val = 0x20485699,
@@ -471,6 +475,7 @@ static struct clk_alpha_pll cam_cc_pll4 = { 
	.vco_table = trion_vco,

	.num_vco = ARRAY_SIZE(trion_vco),

	.type = TRION_PLL,

	.config = &cam_cc_pll4_config,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "cam_cc_pll4",
@@ -2421,14 +2426,11 @@ MODULE_DEVICE_TABLE(of, cam_cc_sm8150_match_table); 


static void cam_cc_sm8150_fixup_sm8150v2(struct regmap *regmap)

{

	clk_trion_pll_configure(&cam_cc_pll0, regmap,

		&cam_cc_pll0_config_sm8150_v2);

	clk_trion_pll_configure(&cam_cc_pll1, regmap,

		&cam_cc_pll1_config_sm8150_v2);

	clk_trion_pll_configure(&cam_cc_pll3, regmap,

		&cam_cc_pll3_config_sm8150_v2);

	clk_trion_pll_configure(&cam_cc_pll4, regmap,

		&cam_cc_pll4_config_sm8150_v2);

	cam_cc_pll0.config = &cam_cc_pll0_config_sm8150_v2;

	cam_cc_pll1.config = &cam_cc_pll1_config_sm8150_v2;

	cam_cc_pll3.config = &cam_cc_pll3_config_sm8150_v2;

	cam_cc_pll4.config = &cam_cc_pll4_config_sm8150_v2;



	cam_cc_ife_0_clk_src.freq_tbl = ftbl_cam_cc_ife_0_clk_src_sm8150_v2;

	cam_cc_ife_0_clk_src.clkr.hw.init->rate_max[VDD_NOMINAL] = 847000000;

	cam_cc_ife_0_clk_src.clkr.hw.init->rate_max[VDD_HIGH] = 950000000;
@@ -2510,11 +2512,11 @@ static int cam_cc_sm8150_probe(struct platform_device *pdev) 
	if (ret)

		return ret;



	clk_trion_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config);

	clk_trion_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config);

	clk_regera_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config);

	clk_trion_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config);

	clk_trion_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config);

	clk_trion_pll_configure(&cam_cc_pll0, regmap, cam_cc_pll0.config);

	clk_trion_pll_configure(&cam_cc_pll1, regmap, cam_cc_pll1.config);

	clk_regera_pll_configure(&cam_cc_pll2, regmap, cam_cc_pll2.config);

	clk_trion_pll_configure(&cam_cc_pll3, regmap, cam_cc_pll3.config);

	clk_trion_pll_configure(&cam_cc_pll4, regmap, cam_cc_pll4.config);



	ret = qcom_cc_really_probe(pdev, &cam_cc_sm8150_desc, regmap);

	if (ret) {

drivers/clk/qcom/dispcc-sm8150.c

+11 −10
Original line number Diff line number Diff line
@@ -204,7 +204,7 @@ static struct pll_vco trion_vco[] = { 
	{ 249600000, 2000000000, 0 },

};



static const struct alpha_pll_config disp_cc_pll0_config = {

static struct alpha_pll_config disp_cc_pll0_config = {

	.l = 0x47,

	.alpha = 0xE000,

	.config_ctl_val = 0x20485699,
@@ -218,7 +218,7 @@ static const struct alpha_pll_config disp_cc_pll0_config = { 
	.user_ctl_hi1_val = 0x000000D0,

};



static const struct alpha_pll_config disp_cc_pll0_config_sm8150_v2 = {

static struct alpha_pll_config disp_cc_pll0_config_sm8150_v2 = {

	.l = 0x47,

	.alpha = 0xE000,

	.config_ctl_val = 0x20485699,
@@ -234,6 +234,7 @@ static struct clk_alpha_pll disp_cc_pll0 = { 
	.vco_table = trion_vco,

	.num_vco = ARRAY_SIZE(trion_vco),

	.type = TRION_PLL,

	.config = &disp_cc_pll0_config,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "disp_cc_pll0",
@@ -251,7 +252,7 @@ static struct clk_alpha_pll disp_cc_pll0 = { 
	},

};



static const struct alpha_pll_config disp_cc_pll1_config = {

static struct alpha_pll_config disp_cc_pll1_config = {

	.l = 0x1F,

	.alpha = 0x4000,

	.config_ctl_val = 0x20485699,
@@ -265,7 +266,7 @@ static const struct alpha_pll_config disp_cc_pll1_config = { 
	.user_ctl_hi1_val = 0x000000D0,

};



static const struct alpha_pll_config disp_cc_pll1_config_sm8150_v2 = {

static struct alpha_pll_config disp_cc_pll1_config_sm8150_v2 = {

	.l = 0x1F,

	.alpha = 0x4000,

	.config_ctl_val = 0x20485699,
@@ -281,6 +282,7 @@ static struct clk_alpha_pll disp_cc_pll1 = { 
	.vco_table = trion_vco,

	.num_vco = ARRAY_SIZE(trion_vco),

	.type = TRION_PLL,

	.config = &disp_cc_pll1_config,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "disp_cc_pll1",
@@ -1553,10 +1555,9 @@ MODULE_DEVICE_TABLE(of, disp_cc_sm8150_match_table); 


static void disp_cc_sm8150_fixup_sm8150v2(struct regmap *regmap)

{

	clk_trion_pll_configure(&disp_cc_pll0, regmap,

		&disp_cc_pll0_config_sm8150_v2);

	clk_trion_pll_configure(&disp_cc_pll1, regmap,

		&disp_cc_pll1_config_sm8150_v2);

	disp_cc_pll0.config = &disp_cc_pll0_config_sm8150_v2;

	disp_cc_pll1.config = &disp_cc_pll1_config_sm8150_v2;



	disp_cc_mdss_dp_pixel1_clk_src.clkr.hw.init->rate_max[VDD_LOW_L1] =

		337500;

	disp_cc_mdss_dp_pixel1_clk_src.clkr.hw.init->rate_max[VDD_NOMINAL] =
@@ -1653,8 +1654,8 @@ static int disp_cc_sm8150_probe(struct platform_device *pdev) 
	if (ret)

		return ret;



	clk_trion_pll_configure(&disp_cc_pll0, regmap, &disp_cc_pll0_config);

	clk_trion_pll_configure(&disp_cc_pll1, regmap, &disp_cc_pll1_config);

	clk_trion_pll_configure(&disp_cc_pll0, regmap, disp_cc_pll0.config);

	clk_trion_pll_configure(&disp_cc_pll1, regmap, disp_cc_pll1.config);



	/* Enable clock gating for DSI and MDP clocks */

	regmap_update_bits(regmap, DISP_CC_MISC_CMD, 0x10, 0x10);

drivers/clk/qcom/gpucc-sm8150.c

+5 −4
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2018, The Linux Foundation. All rights reserved.

 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -72,7 +72,7 @@ static struct pll_vco trion_vco[] = { 
	{ 249600000, 2000000000, 0 },

};



static const struct alpha_pll_config gpu_cc_pll1_config = {

static struct alpha_pll_config gpu_cc_pll1_config = {

	.l = 0x1A,

	.alpha = 0xAAA,

	.config_ctl_val = 0x20485699,
@@ -90,6 +90,7 @@ static struct clk_alpha_pll gpu_cc_pll1 = { 
	.offset = 0x100,

	.vco_table = trion_vco,

	.num_vco = ARRAY_SIZE(trion_vco),

	.config = &gpu_cc_pll1_config,

	.type = TRION_PLL,

	.clkr = {

		.hw.init = &(struct clk_init_data){
@@ -484,8 +485,6 @@ static int gpu_cc_sm8150_probe(struct platform_device *pdev) 
		return PTR_ERR(vdd_mx.regulator[0]);

	}



	clk_trion_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);



	gpu_cc_sm8150_fixup(pdev);



	for (i = 0; i < ARRAY_SIZE(gpu_cc_sm8150_hws); i++) {
@@ -494,6 +493,8 @@ static int gpu_cc_sm8150_probe(struct platform_device *pdev) 
			return PTR_ERR(clk);

	}



	clk_trion_pll_configure(&gpu_cc_pll1, regmap, gpu_cc_pll1.config);



	ret = qcom_cc_really_probe(pdev, &gpu_cc_sm8150_desc, regmap);

	if (ret) {

		dev_err(&pdev->dev, "Failed to register GPU CC clocks\n");

drivers/clk/qcom/scc-sm8150.c

+7 −5
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2018, The Linux Foundation. All rights reserved.

 * Copyright (c) 2018-2019, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -75,7 +75,7 @@ static struct pll_vco trion_vco[] = { 
	{ 249600000, 2000000000, 0 },

};



static const struct alpha_pll_config scc_pll_config = {

static struct alpha_pll_config scc_pll_config = {

	.l = 0x1F,

	.alpha = 0x4000,

	.config_ctl_val = 0x20485699,
@@ -89,7 +89,7 @@ static const struct alpha_pll_config scc_pll_config = { 
	.user_ctl_hi1_val = 0x000000D0,

};



static const struct alpha_pll_config scc_pll_config_sm8150_v2 = {

static struct alpha_pll_config scc_pll_config_sm8150_v2 = {

	.l = 0x1E,

	.alpha = 0x0,

	.config_ctl_val = 0x20485699,
@@ -105,6 +105,7 @@ static struct clk_alpha_pll scc_pll = { 
	.vco_table = trion_vco,

	.num_vco = ARRAY_SIZE(trion_vco),

	.type = TRION_PLL,

	.config = &scc_pll_config,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "scc_pll",
@@ -581,7 +582,8 @@ MODULE_DEVICE_TABLE(of, scc_sm8150_match_table); 


static void scc_sm8150_fixup_sm8150v2(struct regmap *regmap)

{

	clk_trion_pll_configure(&scc_pll, regmap, &scc_pll_config_sm8150_v2);

	scc_pll.config = &scc_pll_config_sm8150_v2;



	scc_main_rcg_clk_src.freq_tbl = ftbl_scc_main_rcg_clk_src_sm8150_v2;

	scc_main_rcg_clk_src.clkr.hw.init->rate_max[VDD_MIN] = 96000000;

	scc_main_rcg_clk_src.clkr.hw.init->rate_max[VDD_LOW] = 576000000;
@@ -663,7 +665,7 @@ static int scc_sm8150_probe(struct platform_device *pdev) 
	if (ret)

		return ret;



	clk_trion_pll_configure(&scc_pll, regmap, &scc_pll_config);

	clk_trion_pll_configure(&scc_pll, regmap, scc_pll.config);



	ret = qcom_cc_really_probe(pdev, &scc_sm8150_desc, regmap);

	if (ret) {

drivers/clk/qcom/videocc-sm8150.c

+7 −6
Original line number Diff line number Diff line 
/*

 * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.

 * Copyright (c) 2017-2019, The Linux Foundation. All rights reserved.

 *

 * This program is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License version 2 and
@@ -103,7 +103,7 @@ static struct pll_vco trion_vco[] = { 
	{ 249600000, 2000000000, 0 },

};



static const struct alpha_pll_config video_pll0_config = {

static struct alpha_pll_config video_pll0_config = {

	.l = 0x14,

	.alpha = 0xD555,

	.config_ctl_val = 0x20485699,
@@ -117,7 +117,7 @@ static const struct alpha_pll_config video_pll0_config = { 
	.user_ctl_hi1_val = 0x000000D0,

};



static const struct alpha_pll_config video_pll0_config_sm8150_v2 = {

static struct alpha_pll_config video_pll0_config_sm8150_v2 = {

	.l = 0x14,

	.alpha = 0xD555,

	.config_ctl_val = 0x20485699,
@@ -133,6 +133,7 @@ static struct clk_alpha_pll video_pll0 = { 
	.vco_table = trion_vco,

	.num_vco = ARRAY_SIZE(trion_vco),

	.type = TRION_PLL,

	.config = &video_pll0_config,

	.clkr = {

		.hw.init = &(struct clk_init_data){

			.name = "video_pll0",
@@ -320,8 +321,8 @@ MODULE_DEVICE_TABLE(of, video_cc_sm8150_match_table); 


static void video_cc_sm8150_fixup_sm8150v2(struct regmap *regmap)

{

	clk_trion_pll_configure(&video_pll0, regmap,

		&video_pll0_config_sm8150_v2);

	video_pll0.config = &video_pll0_config_sm8150_v2;



	video_cc_iris_clk_src.freq_tbl = ftbl_video_cc_iris_clk_src_sm8150_v2;

	video_cc_iris_clk_src.clkr.hw.init->rate_max[VDD_LOWER] = 240000000;

	video_cc_iris_clk_src.clkr.hw.init->rate_max[VDD_LOW] = 338000000;
@@ -392,7 +393,7 @@ static int video_cc_sm8150_probe(struct platform_device *pdev) 
	if (ret)

		return ret;



	clk_trion_pll_configure(&video_pll0, regmap, &video_pll0_config);

	clk_trion_pll_configure(&video_pll0, regmap, video_pll0.config);



	ret = qcom_cc_really_probe(pdev, &video_cc_sm8150_desc, regmap);

	if (ret) {