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Commit 5d6b3d73 authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge "drm/msm/sde: add dgm csc12 support"

parents df4931b2 eb30b3b4

Documentation/devicetree/bindings/display/msm/sde.txt

+10 −0
Original line number Diff line number Diff line
@@ -214,6 +214,8 @@ Optional properties: 
				-- qcom,sde-vig-memcolor: offset and version of PA memcolor hardware

				-- qcom,sde-vig-gamut: offset and version of 3D LUT Gamut hardware

				-- qcom,sde-vig-igc: offset and version of 1D LUT IGC hardware

				-- qcom,sde-vig-inverse-pma: Boolean property to indicate if

				inverse PMA feature is available on VIG pipe

- qcom,sde-sspp-dma-blocks:	A node that lists the blocks inside the DMA hardware. There

				can be more than one instance of this binding, in which case the

				entry would be appended with dgm entry index. Each entry will
@@ -224,6 +226,9 @@ Optional properties: 
				-- dgm@0

				-- qcom,sde-dma-igc: offset and version of DMA IGC

				-- qcom,sde-dma-gc: offset and version of DMA GC

				-- qcom,sde-dma-inverse-pma: Boolean property to indicate if

				inverse PMA feature is available on DMA pipe

				-- qcom,sde-dma-csc-off: offset of CSC hardware

- qcom,sde-sspp-rgb-blocks:	A node that lists the blocks inside the RGB hardware. The

				block entries will contain the offset and version (if needed)

				of each feature block. The presence of a block entry
@@ -680,16 +685,21 @@ Example: 
        qcom,sde-vig-hsic = <0x200 0x00010000>;

        qcom,sde-vig-memcolor = <0x200 0x00010000>;

        qcom,sde-vig-pcc = <0x1780 0x00010000>;

        qcom,sde-vig-inverse-pma;

    };



    qcom,sde-sspp-dma-blocks {

	dgm@0 {

		qcom,sde-dma-igc = <0x400 0x00050000>;

		qcom,sde-dma-gc = <0x600 0x00050000>;

		qcom,sde-dma-inverse-pma;

		qcom,sde-dma-csc-off = <0x200>;

	}

	dgm@1 {

		qcom,sde-dma-igc = <0x1400 0x00050000>;

		qcom,sde-dma-gc = <0x600 0x00050000>;

		qcom,sde-dma-inverse-pma;

		qcom,sde-dma-csc-off = <0x1200>;

	}

    };

drivers/gpu/drm/msm/msm_drv.h

+2 −0
Original line number Diff line number Diff line
@@ -84,6 +84,7 @@ struct msm_file_private { 
enum msm_mdp_plane_property {

	/* blob properties, always put these first */

	PLANE_PROP_CSC_V1,

	PLANE_PROP_CSC_DMA_V1,

	PLANE_PROP_INFO,

	PLANE_PROP_SCALER_LUT_ED,

	PLANE_PROP_SCALER_LUT_CIR,
@@ -121,6 +122,7 @@ enum msm_mdp_plane_property { 
	PLANE_PROP_SCALER_V1,

	PLANE_PROP_SCALER_V2,

	PLANE_PROP_ROT_OUT_FB,

	PLANE_PROP_INVERSE_PMA,



	/* enum/bitmask properties */

	PLANE_PROP_BLEND_OP,

drivers/gpu/drm/msm/sde/sde_hw_catalog.c

+28 −3
Original line number Diff line number Diff line
@@ -216,6 +216,7 @@ enum { 
	VIG_PCC_PROP,

	VIG_GAMUT_PROP,

	VIG_IGC_PROP,

	VIG_INVERSE_PMA,

	VIG_PROP_MAX,

};
@@ -229,6 +230,8 @@ enum { 
enum {

	DMA_IGC_PROP,

	DMA_GC_PROP,

	DMA_DGM_INVERSE_PMA,

	DMA_CSC_OFF,

	DMA_PROP_MAX,

};
@@ -507,6 +510,7 @@ static struct sde_prop_type vig_prop[] = { 
	{VIG_PCC_PROP, "qcom,sde-vig-pcc", false, PROP_TYPE_U32_ARRAY},

	{VIG_GAMUT_PROP, "qcom,sde-vig-gamut", false, PROP_TYPE_U32_ARRAY},

	{VIG_IGC_PROP, "qcom,sde-vig-igc", false, PROP_TYPE_U32_ARRAY},

	{VIG_INVERSE_PMA, "qcom,sde-vig-inverse-pma", false, PROP_TYPE_BOOL},

};



static struct sde_prop_type rgb_prop[] = {
@@ -518,6 +522,9 @@ static struct sde_prop_type rgb_prop[] = { 
static struct sde_prop_type dma_prop[] = {

	{DMA_IGC_PROP, "qcom,sde-dma-igc", false, PROP_TYPE_U32_ARRAY},

	{DMA_GC_PROP, "qcom,sde-dma-gc", false, PROP_TYPE_U32_ARRAY},

	{DMA_DGM_INVERSE_PMA, "qcom,sde-dma-inverse-pma", false,

		PROP_TYPE_BOOL},

	{DMA_CSC_OFF, "qcom,sde-dma-csc-off", false, PROP_TYPE_U32},

};



static struct sde_prop_type ctl_prop[] = {
@@ -1064,6 +1071,9 @@ static void _sde_sspp_setup_vig(struct sde_mdss_cfg *sde_cfg, 
		set_bit(SDE_SSPP_VIG_IGC, &sspp->features);

	}



	if (PROP_VALUE_ACCESS(prop_value, VIG_INVERSE_PMA, 0))

		set_bit(SDE_SSPP_INVERSE_PMA, &sspp->features);



	sblk->format_list = sde_cfg->vig_formats;

	sblk->virt_format_list = sde_cfg->dma_formats;

}
@@ -1167,6 +1177,7 @@ static void _sde_sspp_setup_dma(struct sde_mdss_cfg *sde_cfg, 


	sblk->num_igc_blk = dgm_count;

	sblk->num_gc_blk = dgm_count;

	sblk->num_dgm_csc_blk = dgm_count;

	for (i = 0; i < dgm_count; i++) {

		if (prop_exists[i][DMA_IGC_PROP]) {

			sblk->igc_blk[i].id = SDE_SSPP_DMA_IGC;
@@ -1191,6 +1202,19 @@ static void _sde_sspp_setup_dma(struct sde_mdss_cfg *sde_cfg, 
			sblk->gc_blk[i].len = 0;

			set_bit(SDE_SSPP_DMA_GC, &sspp->features);

		}



		if (PROP_VALUE_ACCESS(&prop_value[i * DMA_PROP_MAX],

			DMA_DGM_INVERSE_PMA, 0))

			set_bit(SDE_SSPP_DGM_INVERSE_PMA, &sspp->features);



		if (prop_exists[i][DMA_CSC_OFF]) {

			sblk->dgm_csc_blk[i].id = SDE_SSPP_DGM_CSC;

			snprintf(sblk->csc_blk.name, SDE_HW_BLK_NAME_LEN,

				"sspp_dgm_csc%u", sspp->id - SSPP_DMA0);

			set_bit(SDE_SSPP_DGM_CSC, &sspp->features);

			sblk->dgm_csc_blk[i].base = PROP_VALUE_ACCESS(

				&prop_value[i * DMA_PROP_MAX], DMA_CSC_OFF, 0);

		}

	}

}
@@ -1299,8 +1323,10 @@ static int sde_sspp_parse_dt(struct device_node *np, 
			dgm_prop_value = kzalloc(dgm_count * DMA_PROP_MAX *

					sizeof(struct sde_prop_value),

					GFP_KERNEL);

			if (!dgm_prop_value)

				return -ENOMEM;

			if (!dgm_prop_value) {

				rc = -ENOMEM;

				goto end;

			}

			for (i = 0; i < dgm_count; i++)

				sde_dgm_parse_dt(snp, i,

					&dgm_prop_value[i * DMA_PROP_MAX],
@@ -1355,7 +1381,6 @@ static int sde_sspp_parse_dt(struct device_node *np, 
			_sde_sspp_setup_cursor(sde_cfg, sspp, sblk, NULL,

								&cursor_count);

		} else if (!strcmp(type, "dma")) {

			/* No prop values for DMA pipes */

			_sde_sspp_setup_dma(sde_cfg, sspp, sblk,

				dgm_prop_exists, dgm_prop_value, &dma_count,

				dgm_count);

drivers/gpu/drm/msm/sde/sde_hw_catalog.h

+10 −1
Original line number Diff line number Diff line
@@ -144,6 +144,9 @@ enum { 
 * @SDE_SSPP_VIG_GAMUT,      VIG 3D LUT Gamut

 * @SDE_SSPP_DMA_IGC,        DMA 1D LUT IGC

 * @SDE_SSPP_DMA_GC,         DMA 1D LUT GC

 * @SDE_SSPP_INVERSE_PMA     Alpha unmultiply (PMA) support

 * @SDE_SSPP_DGM_INVERSE_PMA Alpha unmultiply (PMA) support in DGM block

 * @SDE_SSPP_DGM_CSC         Support of color space conversion in DGM block

 * @SDE_SSPP_MAX             maximum value

 */

enum {
@@ -170,6 +173,9 @@ enum { 
	SDE_SSPP_VIG_GAMUT,

	SDE_SSPP_DMA_IGC,

	SDE_SSPP_DMA_GC,

	SDE_SSPP_INVERSE_PMA,

	SDE_SSPP_DGM_INVERSE_PMA,

	SDE_SSPP_DGM_CSC,

	SDE_SSPP_MAX

};
@@ -466,7 +472,8 @@ struct sde_qos_lut_tbl { 
 * @igc_blk: 1D LUT IGC block

 * @num_gc_blk: number of GC block

 * @gc_blk: 1D LUT GC block



 * @num_dgm_csc_blk: number of DGM CSC blocks

 * @dgm_csc_blk: DGM CSC blocks

 * @format_list: Pointer to list of supported formats

 * @virt_format_list: Pointer to list of supported formats for virtual planes

 */
@@ -492,6 +499,8 @@ struct sde_sspp_sub_blks { 
	struct sde_pp_blk igc_blk[SSPP_SUBBLK_COUNT_MAX];

	u32 num_gc_blk;

	struct sde_pp_blk gc_blk[SSPP_SUBBLK_COUNT_MAX];

	u32 num_dgm_csc_blk;

	struct sde_pp_blk dgm_csc_blk[SSPP_SUBBLK_COUNT_MAX];



	const struct sde_format_extended *format_list;

	const struct sde_format_extended *virt_format_list;

drivers/gpu/drm/msm/sde/sde_hw_sspp.c

+74 −0
Original line number Diff line number Diff line
@@ -48,6 +48,11 @@ 
#define SSPP_EXCL_REC_SIZE_REC1            0x184

#define SSPP_EXCL_REC_XY_REC1              0x188



/* SSPP_DGM */

#define SSPP_DGM_OP_MODE                   0x804

#define SSPP_DGM_OP_MODE_REC1              0x1804

#define SSPP_GAMUT_UNMULT_MODE             0x1EA0



#define MDSS_MDP_OP_DEINTERLACE            BIT(22)

#define MDSS_MDP_OP_DEINTERLACE_ODD        BIT(23)

#define MDSS_MDP_OP_IGC_ROM_1              BIT(18)
@@ -985,6 +990,67 @@ static void _setup_layer_ops_colorproc(struct sde_hw_pipe *c, 
	}

}



static void sde_hw_sspp_setup_inverse_pma(struct sde_hw_pipe *ctx,

			enum sde_sspp_multirect_index index, u32 enable)

{

	u32 op_mode = 0;



	if (!ctx || (index == SDE_SSPP_RECT_1))

		return;



	if (enable)

		op_mode |= BIT(0);



	SDE_REG_WRITE(&ctx->hw, SSPP_GAMUT_UNMULT_MODE, op_mode);

}



static void sde_hw_sspp_setup_dgm_inverse_pma(struct sde_hw_pipe *ctx,

			enum sde_sspp_multirect_index index, u32 enable)

{

	u32 offset = SSPP_DGM_OP_MODE;

	u32 op_mode = 0;



	if (!ctx)

		return;



	if (index == SDE_SSPP_RECT_1)

		offset = SSPP_DGM_OP_MODE_REC1;



	op_mode = SDE_REG_READ(&ctx->hw, offset);



	if (enable)

		op_mode |= BIT(0);

	else

		op_mode &= ~BIT(0);



	SDE_REG_WRITE(&ctx->hw, offset, op_mode);

}



static void sde_hw_sspp_setup_dgm_csc(struct sde_hw_pipe *ctx,

		enum sde_sspp_multirect_index index, struct sde_csc_cfg *data)

{

	u32 idx = 0;

	u32 offset;

	u32 op_mode = 0;

	const struct sde_sspp_sub_blks *sblk;



	if (!ctx || !ctx->cap || !ctx->cap->sblk)

		return;



	sblk = ctx->cap->sblk;

	if (index == SDE_SSPP_RECT_1)

		idx = 1;



	offset = sblk->dgm_csc_blk[idx].base;

	if (data) {

		op_mode |= BIT(0);

		sde_hw_csc_matrix_coeff_setup(&ctx->hw,

			offset + CSC_10BIT_OFFSET, data);

	}



	SDE_REG_WRITE(&ctx->hw, offset, op_mode);

}



static void _setup_layer_ops(struct sde_hw_pipe *c,

		unsigned long features)

{
@@ -1014,6 +1080,9 @@ static void _setup_layer_ops(struct sde_hw_pipe *c, 
		test_bit(SDE_SSPP_CSC_10BIT, &features))

		c->ops.setup_csc = sde_hw_sspp_setup_csc;



	if (test_bit(SDE_SSPP_DGM_CSC, &features))

		c->ops.setup_dgm_csc = sde_hw_sspp_setup_dgm_csc;



	if (test_bit(SDE_SSPP_SCALER_QSEED2, &features)) {

		c->ops.setup_sharpening = sde_hw_sspp_setup_sharpening;

		c->ops.setup_scaler = _sde_hw_sspp_setup_scaler;
@@ -1036,6 +1105,11 @@ static void _setup_layer_ops(struct sde_hw_pipe *c, 
		c->ops.setup_cdp = sde_hw_sspp_setup_cdp;



	_setup_layer_ops_colorproc(c, features);



	if (test_bit(SDE_SSPP_DGM_INVERSE_PMA, &features))

		c->ops.setup_inverse_pma = sde_hw_sspp_setup_dgm_inverse_pma;

	else if (test_bit(SDE_SSPP_INVERSE_PMA, &features))

		c->ops.setup_inverse_pma = sde_hw_sspp_setup_inverse_pma;

}



static struct sde_sspp_cfg *_sspp_offset(enum sde_sspp sspp,