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Commit eb30b3b4 authored by Alexander Beykun's avatar Alexander Beykun
Browse files

drm/msm/sde: add dgm csc12 support 



Add csc12 support for DMA pipes. Csc12 block is used
inside DGM block for 12 bit color space conversion.

Change-Id: Iba6b99e7a0779b197a9cf4fd490334991f7448aa
Signed-off-by: default avatarAlexander Beykun <abeykun@codeaurora.org>
parent 28916c92

Documentation/devicetree/bindings/display/msm/sde.txt

+3 −0
Original line number Diff line number Diff line
@@ -228,6 +228,7 @@ Optional properties: 
				-- qcom,sde-dma-gc: offset and version of DMA GC

				-- qcom,sde-dma-inverse-pma: Boolean property to indicate if

				inverse PMA feature is available on DMA pipe

				-- qcom,sde-dma-csc-off: offset of CSC hardware

- qcom,sde-sspp-rgb-blocks:	A node that lists the blocks inside the RGB hardware. The

				block entries will contain the offset and version (if needed)

				of each feature block. The presence of a block entry
@@ -692,11 +693,13 @@ Example: 
		qcom,sde-dma-igc = <0x400 0x00050000>;

		qcom,sde-dma-gc = <0x600 0x00050000>;

		qcom,sde-dma-inverse-pma;

		qcom,sde-dma-csc-off = <0x200>;

	}

	dgm@1 {

		qcom,sde-dma-igc = <0x1400 0x00050000>;

		qcom,sde-dma-gc = <0x600 0x00050000>;

		qcom,sde-dma-inverse-pma;

		qcom,sde-dma-csc-off = <0x1200>;

	}

    };

drivers/gpu/drm/msm/msm_drv.h

+1 −0
Original line number Diff line number Diff line
@@ -84,6 +84,7 @@ struct msm_file_private { 
enum msm_mdp_plane_property {

	/* blob properties, always put these first */

	PLANE_PROP_CSC_V1,

	PLANE_PROP_CSC_DMA_V1,

	PLANE_PROP_INFO,

	PLANE_PROP_SCALER_LUT_ED,

	PLANE_PROP_SCALER_LUT_CIR,

drivers/gpu/drm/msm/sde/sde_hw_catalog.c

+11 −1
Original line number Diff line number Diff line
@@ -231,6 +231,7 @@ enum { 
	DMA_IGC_PROP,

	DMA_GC_PROP,

	DMA_DGM_INVERSE_PMA,

	DMA_CSC_OFF,

	DMA_PROP_MAX,

};
@@ -523,6 +524,7 @@ static struct sde_prop_type dma_prop[] = { 
	{DMA_GC_PROP, "qcom,sde-dma-gc", false, PROP_TYPE_U32_ARRAY},

	{DMA_DGM_INVERSE_PMA, "qcom,sde-dma-inverse-pma", false,

		PROP_TYPE_BOOL},

	{DMA_CSC_OFF, "qcom,sde-dma-csc-off", false, PROP_TYPE_U32},

};



static struct sde_prop_type ctl_prop[] = {
@@ -1175,6 +1177,7 @@ static void _sde_sspp_setup_dma(struct sde_mdss_cfg *sde_cfg, 


	sblk->num_igc_blk = dgm_count;

	sblk->num_gc_blk = dgm_count;

	sblk->num_dgm_csc_blk = dgm_count;

	for (i = 0; i < dgm_count; i++) {

		if (prop_exists[i][DMA_IGC_PROP]) {

			sblk->igc_blk[i].id = SDE_SSPP_DMA_IGC;
@@ -1204,6 +1207,14 @@ static void _sde_sspp_setup_dma(struct sde_mdss_cfg *sde_cfg, 
			DMA_DGM_INVERSE_PMA, 0))

			set_bit(SDE_SSPP_DGM_INVERSE_PMA, &sspp->features);



		if (prop_exists[i][DMA_CSC_OFF]) {

			sblk->dgm_csc_blk[i].id = SDE_SSPP_DGM_CSC;

			snprintf(sblk->csc_blk.name, SDE_HW_BLK_NAME_LEN,

				"sspp_dgm_csc%u", sspp->id - SSPP_DMA0);

			set_bit(SDE_SSPP_DGM_CSC, &sspp->features);

			sblk->dgm_csc_blk[i].base = PROP_VALUE_ACCESS(

				&prop_value[i * DMA_PROP_MAX], DMA_CSC_OFF, 0);

		}

	}

}
@@ -1370,7 +1381,6 @@ static int sde_sspp_parse_dt(struct device_node *np, 
			_sde_sspp_setup_cursor(sde_cfg, sspp, sblk, NULL,

								&cursor_count);

		} else if (!strcmp(type, "dma")) {

			/* No prop values for DMA pipes */

			_sde_sspp_setup_dma(sde_cfg, sspp, sblk,

				dgm_prop_exists, dgm_prop_value, &dma_count,

				dgm_count);

drivers/gpu/drm/msm/sde/sde_hw_catalog.h

+6 −1
Original line number Diff line number Diff line
@@ -144,6 +144,7 @@ enum { 
 * @SDE_SSPP_DMA_GC,         DMA 1D LUT GC

 * @SDE_SSPP_INVERSE_PMA     Alpha unmultiply (PMA) support

 * @SDE_SSPP_DGM_INVERSE_PMA Alpha unmultiply (PMA) support in DGM block

 * @SDE_SSPP_DGM_CSC         Support of color space conversion in DGM block

 * @SDE_SSPP_MAX             maximum value

 */

enum {
@@ -172,6 +173,7 @@ enum { 
	SDE_SSPP_DMA_GC,

	SDE_SSPP_INVERSE_PMA,

	SDE_SSPP_DGM_INVERSE_PMA,

	SDE_SSPP_DGM_CSC,

	SDE_SSPP_MAX

};
@@ -466,7 +468,8 @@ struct sde_qos_lut_tbl { 
 * @igc_blk: 1D LUT IGC block

 * @num_gc_blk: number of GC block

 * @gc_blk: 1D LUT GC block



 * @num_dgm_csc_blk: number of DGM CSC blocks

 * @dgm_csc_blk: DGM CSC blocks

 * @format_list: Pointer to list of supported formats

 * @virt_format_list: Pointer to list of supported formats for virtual planes

 */
@@ -492,6 +495,8 @@ struct sde_sspp_sub_blks { 
	struct sde_pp_blk igc_blk[SSPP_SUBBLK_COUNT_MAX];

	u32 num_gc_blk;

	struct sde_pp_blk gc_blk[SSPP_SUBBLK_COUNT_MAX];

	u32 num_dgm_csc_blk;

	struct sde_pp_blk dgm_csc_blk[SSPP_SUBBLK_COUNT_MAX];



	const struct sde_format_extended *format_list;

	const struct sde_format_extended *virt_format_list;

drivers/gpu/drm/msm/sde/sde_hw_sspp.c

+28 −0
Original line number Diff line number Diff line
@@ -1026,6 +1026,31 @@ static void sde_hw_sspp_setup_dgm_inverse_pma(struct sde_hw_pipe *ctx, 
	SDE_REG_WRITE(&ctx->hw, offset, op_mode);

}



static void sde_hw_sspp_setup_dgm_csc(struct sde_hw_pipe *ctx,

		enum sde_sspp_multirect_index index, struct sde_csc_cfg *data)

{

	u32 idx = 0;

	u32 offset;

	u32 op_mode = 0;

	const struct sde_sspp_sub_blks *sblk;



	if (!ctx || !ctx->cap || !ctx->cap->sblk)

		return;



	sblk = ctx->cap->sblk;

	if (index == SDE_SSPP_RECT_1)

		idx = 1;



	offset = sblk->dgm_csc_blk[idx].base;

	if (data) {

		op_mode |= BIT(0);

		sde_hw_csc_matrix_coeff_setup(&ctx->hw,

			offset + CSC_10BIT_OFFSET, data);

	}



	SDE_REG_WRITE(&ctx->hw, offset, op_mode);

}



static void _setup_layer_ops(struct sde_hw_pipe *c,

		unsigned long features)

{
@@ -1055,6 +1080,9 @@ static void _setup_layer_ops(struct sde_hw_pipe *c, 
		test_bit(SDE_SSPP_CSC_10BIT, &features))

		c->ops.setup_csc = sde_hw_sspp_setup_csc;



	if (test_bit(SDE_SSPP_DGM_CSC, &features))

		c->ops.setup_dgm_csc = sde_hw_sspp_setup_dgm_csc;



	if (test_bit(SDE_SSPP_SCALER_QSEED2, &features)) {

		c->ops.setup_sharpening = sde_hw_sspp_setup_sharpening;

		c->ops.setup_scaler = _sde_hw_sspp_setup_scaler;