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Commit 56f5f590 authored by Michael Hennerich's avatar Michael Hennerich Committed by Bryan Wu
Browse files

Blackfin arch: Fix Bug - System with EMAC driver enabled - Core not idling



 - Disable all bits in SIC_IWR unless we are going into a real (DPMC)
   power saving mode. Any Interrupt can wake the core form it's idle state.

 - Remove deep sleep mode as it is not going to be used anywhere:
   We support sleep, sleep deeper and hibernate.

Signed-off-by: default avatarMichael Hennerich <michael.hennerich@analog.com>
Signed-off-by: default avatarBryan Wu <cooloney@kernel.org>
parent 15b07536
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+0 −7
Original line number Diff line number Diff line
@@ -183,13 +183,6 @@ ENTRY(_start_dma_code)
	[P2] = R1;
	SSYNC;

	p0.h = hi(SIC_IWR0);
	p0.l = lo(SIC_IWR0);
	r0.l = lo(IWR_ENABLE_ALL);
	r0.h = hi(IWR_ENABLE_ALL);
	[p0] = r0;
	SSYNC;

	RTS;
ENDPROC(_start_dma_code)
#endif /* CONFIG_BFIN_KERNEL_CLOCK */
+0 −7
Original line number Diff line number Diff line
@@ -177,13 +177,6 @@ ENTRY(_start_dma_code)
	[P2] = R1;
	SSYNC;

	p0.h = hi(SIC_IWR);
	p0.l = lo(SIC_IWR);
	r0.l = lo(IWR_ENABLE_ALL);
	r0.h = hi(IWR_ENABLE_ALL);
	[p0] = r0;
	SSYNC;

	RTS;
ENDPROC(_start_dma_code)
#endif /* CONFIG_BFIN_KERNEL_CLOCK */
+0 −7
Original line number Diff line number Diff line
@@ -197,13 +197,6 @@ ENTRY(_start_dma_code)
	[P2] = R1;
	SSYNC;

	p0.h = hi(SIC_IWR);
	p0.l = lo(SIC_IWR);
	r0.l = lo(IWR_ENABLE_ALL);
	r0.h = hi(IWR_ENABLE_ALL);
	[p0] = r0;
	SSYNC;

	RTS;
ENDPROC(_start_dma_code)
#endif /* CONFIG_BFIN_KERNEL_CLOCK */
+0 −7
Original line number Diff line number Diff line
@@ -201,13 +201,6 @@ ENTRY(_start_dma_code)
	SSYNC;
#endif

	p0.h = hi(SIC_IWR0);
	p0.l = lo(SIC_IWR0);
	r0.l = lo(IWR_ENABLE_ALL);
	r0.h = hi(IWR_ENABLE_ALL);
	[p0] = r0;
	SSYNC;

	RTS;
ENDPROC(_start_dma_code)
#endif /* CONFIG_BFIN_KERNEL_CLOCK */
+0 −56
Original line number Diff line number Diff line
@@ -78,62 +78,6 @@ ENTRY(_hibernate_mode)
	jump .Lforever;
ENDPROC(_hibernate_mode)

ENTRY(_deep_sleep)
	[--SP] = ( R7:0, P5:0 );
	[--SP] =  RETS;

	CLI R4;

	R0 = IWR_ENABLE(0);
	R1 = IWR_DISABLE_ALL;
	R2 = IWR_DISABLE_ALL;

	call _set_sic_iwr;

	call _set_dram_srfs;

	/* Clear all the interrupts,bits sticky */
	R0 = 0xFFFF (Z);
	call _set_rtc_istat

	P0.H = hi(PLL_CTL);
	P0.L = lo(PLL_CTL);
	R0 = W[P0](z);
	BITSET (R0, 5);
	W[P0] = R0.L;

	call _test_pll_locked;

	SSYNC;
	IDLE;

	call _unset_dram_srfs;

	call _test_pll_locked;

	R0 = IWR_ENABLE(0);
	R1 = IWR_DISABLE_ALL;
	R2 = IWR_DISABLE_ALL;

	call _set_sic_iwr;

	P0.H = hi(PLL_CTL);
	P0.L = lo(PLL_CTL);
	R0 = w[p0](z);
	BITCLR (R0, 3);
	BITCLR (R0, 5);
	BITCLR (R0, 8);
	w[p0] = R0;
	IDLE;
	call _test_pll_locked;

	STI R4;

	RETS = [SP++];
	( R7:0, P5:0 ) = [SP++];
	RTS;
ENDPROC(_deep_sleep)

ENTRY(_sleep_deeper)
	[--SP] = ( R7:0, P5:0 );
	[--SP] =  RETS;
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