Loading arch/arm64/boot/dts/qcom/sm6150.dtsi +3 −3 Original line number Diff line number Diff line Loading @@ -744,7 +744,7 @@ mbox-names = "qdss_clk"; }; clock_gcc: qcom,gcc { clock_gcc: qcom,gcc@100000 { compatible = "qcom,gcc-sm6150", "syscon"; reg = <0x100000 0x1f0000>; reg-names = "cc_base"; Loading @@ -754,7 +754,7 @@ #reset-cells = <1>; }; clock_videocc: qcom,videocc { clock_videocc: qcom,videocc@ab00000 { compatible = "qcom,videocc-sm6150", "syscon"; reg = <0xab00000 0x10000>; reg-names = "cc_base"; Loading @@ -777,7 +777,7 @@ #reset-cells = <1>; }; clock_gpucc: qcom,gpupcc { clock_gpucc: qcom,gpupcc@5090000 { compatible = "qcom,gpucc-sm6150", "syscon"; reg = <0x5090000 0x9000>; reg-names = "cc_base"; Loading Loading
arch/arm64/boot/dts/qcom/sm6150.dtsi +3 −3 Original line number Diff line number Diff line Loading @@ -744,7 +744,7 @@ mbox-names = "qdss_clk"; }; clock_gcc: qcom,gcc { clock_gcc: qcom,gcc@100000 { compatible = "qcom,gcc-sm6150", "syscon"; reg = <0x100000 0x1f0000>; reg-names = "cc_base"; Loading @@ -754,7 +754,7 @@ #reset-cells = <1>; }; clock_videocc: qcom,videocc { clock_videocc: qcom,videocc@ab00000 { compatible = "qcom,videocc-sm6150", "syscon"; reg = <0xab00000 0x10000>; reg-names = "cc_base"; Loading @@ -777,7 +777,7 @@ #reset-cells = <1>; }; clock_gpucc: qcom,gpupcc { clock_gpucc: qcom,gpupcc@5090000 { compatible = "qcom,gpucc-sm6150", "syscon"; reg = <0x5090000 0x9000>; reg-names = "cc_base"; Loading