Loading arch/arm64/boot/dts/qcom/sm8150-v2.dtsi +22 −0 Original line number Diff line number Diff line Loading @@ -43,6 +43,28 @@ }; #include "msm-arm-smmu-sm8150-v2.dtsi" &pcie0 { reg = <0x1c00000 0x4000>, <0x1c06000 0x1000>, <0x60000000 0xf1d>, <0x60000f20 0xa8>, <0x60001000 0x1000>, <0x60100000 0x100000>, <0x60200000 0x100000>, <0x60300000 0x3d00000>; }; &pcie1 { reg = <0x1c08000 0x4000>, <0x1c0e000 0x2000>, <0x40000000 0xf1d>, <0x40000f20 0xa8>, <0x40001000 0x1000>, <0x40100000 0x100000>, <0x40200000 0x100000>, <0x40300000 0x1fd00000>; }; &msm_vidc { qcom,allowed-clock-rates = <240000000 338000000 365000000 444000000 533000000>; Loading Loading
arch/arm64/boot/dts/qcom/sm8150-v2.dtsi +22 −0 Original line number Diff line number Diff line Loading @@ -43,6 +43,28 @@ }; #include "msm-arm-smmu-sm8150-v2.dtsi" &pcie0 { reg = <0x1c00000 0x4000>, <0x1c06000 0x1000>, <0x60000000 0xf1d>, <0x60000f20 0xa8>, <0x60001000 0x1000>, <0x60100000 0x100000>, <0x60200000 0x100000>, <0x60300000 0x3d00000>; }; &pcie1 { reg = <0x1c08000 0x4000>, <0x1c0e000 0x2000>, <0x40000000 0xf1d>, <0x40000f20 0xa8>, <0x40001000 0x1000>, <0x40100000 0x100000>, <0x40200000 0x100000>, <0x40300000 0x1fd00000>; }; &msm_vidc { qcom,allowed-clock-rates = <240000000 338000000 365000000 444000000 533000000>; Loading