[ARM SMP] Ensure secondary CPUs have a clean TLB

Since ARMv6 CPUs will not flush the TLB on context switches, it is
possible that we may end up with some global TLB entries remaining
present, eventually upsetting userspace.  Explicitly flush the
entire TLB on secondary CPUs as they startup, after we have switched
to the init_mm page tables.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>