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Commit 4c81e7ee authored by Linux Build Service Account's avatar Linux Build Service Account Committed by Gerrit - the friendly Code Review server
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Merge changes I2cfdd472,Ib61f5376 into msm-4.14 

* changes:
  clk: qcom: clk-alpha-pll: Use a custom recalc_rate callback for Regera PLL
  clk: qcom: clk-alpha-pll: Do not poll LOCK_DET bit while PLL is disabled
parents 08abfdc3 cc4ee976

drivers/clk/qcom/clk-alpha-pll.c

+22 −2
Original line number Diff line number Diff line
@@ -1199,7 +1199,7 @@ static int clk_regera_pll_set_rate(struct clk_hw *hw, unsigned long rate, 
{

	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);

	unsigned long rrate;

	u32 l, off = pll->offset;

	u32 l, regval, off = pll->offset;

	u64 a;

	int ret;
@@ -1217,6 +1217,13 @@ static int clk_regera_pll_set_rate(struct clk_hw *hw, unsigned long rate, 
	regmap_write(pll->clkr.regmap, off + PLL_ALPHA_VAL, a);

	regmap_write(pll->clkr.regmap, off + PLL_L_VAL, l);



	/* Return early if the PLL is disabled */

	ret = regmap_read(pll->clkr.regmap, off + REGERA_PLL_OPMODE, &regval);

	if (ret)

		return ret;

	else if (regval == REGERA_PLL_OFF)

		return 0;



	/* Wait before polling for the frequency latch */

	udelay(5);
@@ -1229,6 +1236,19 @@ static int clk_regera_pll_set_rate(struct clk_hw *hw, unsigned long rate, 
	return 0;

}



static unsigned long

clk_regera_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)

{

	u32 l, frac;

	u64 prate = parent_rate;

	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);

	u32 off = pll->offset;



	regmap_read(pll->clkr.regmap, off + PLL_L_VAL, &l);

	regmap_read(pll->clkr.regmap, off + PLL_ALPHA_VAL, &frac);



	return alpha_pll_calc_rate(pll, prate, l, frac);

}



static void clk_regera_pll_list_registers(struct seq_file *f, struct clk_hw *hw)

{
@@ -1304,7 +1324,7 @@ const struct clk_ops clk_regera_pll_ops = { 
	.enable = clk_regera_pll_enable,

	.disable = clk_regera_pll_disable,

	.is_enabled = clk_alpha_pll_is_enabled,

	.recalc_rate = clk_alpha_pll_recalc_rate,

	.recalc_rate = clk_regera_pll_recalc_rate,

	.round_rate = clk_alpha_pll_round_rate,

	.set_rate = clk_regera_pll_set_rate,

	.list_registers = clk_regera_pll_list_registers,