Merge "clk: qcom: clk-alpha-pll: Avoid reconfiguring Trion and Regera PLLs" (49579998) · Commits · e / devices / android_kernel_oneplus_sm8150

drivers/clk/qcom/clk-alpha-pll.c

+7 −12

Original line number	Diff line number	Diff line
		@@ -724,23 +724,15 @@ int clk_trion_pll_configure(struct clk_alpha_pll pll, struct regmap regmap,
		{
		int ret = 0;

		if (pll->inited)
		return ret;

		if (trion_pll_is_enabled(pll, regmap)) {
		pr_warn("PLL is already enabled. Skipping configuration.\n");
		pll->inited = true;
		return ret;
		}

		/*
		* Disable the PLL if it's already been initialized. Not doing so might
		* lead to the PLL running with the old frequency configuration.
		*/
		if (pll->inited) {
		ret = regmap_update_bits(regmap, pll->offset + PLL_MODE,
		PLL_RESET_N, 0);
		if (ret)
		return ret;
		}

		if (config->l)
		regmap_write(regmap, pll->offset + PLL_L_VAL,
		config->l);
		@@ -1032,7 +1024,10 @@ int clk_regera_pll_configure(struct clk_alpha_pll pll, struct regmap regmap,
		const struct alpha_pll_config *config)
		{
		u32 mode_regval;
		int ret;
		int ret = 0;

		if (pll->inited)
		return ret;

		ret = regmap_read(regmap, pll->offset + PLL_MODE, &mode_regval);
		if (ret)

+2 −2

Original line number	Diff line number	Diff line
		@@ -603,9 +603,9 @@ static int enable_npu_crc(struct regmap *regmap)
		{
		int ret = 0;

		/* Set npu_cc_cal_cp_clk to a safe frequency */
		/* Set npu_cc_cal_cp_clk to the lowest supported frequency */
		clk_set_rate(npu_cc_cal_dp_clk.clkr.hw.clk,
		npu_cc_cal_dp_clk_src.clkr.hw.init->rate_max[VDD_MIN]);
		clk_round_rate(npu_cc_cal_dp_clk_src.clkr.hw.clk, 1));
		/* Turn on the NPU GDSC */
		ret = regulator_enable(vdd_gdsc);
		if (ret) {