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Commit 423eebbb authored by qctecmdr's avatar qctecmdr Committed by Gerrit - the friendly Code Review server
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Merge "arm64/sve: System register and exception syndrome definitions"

parents dca8adfc c38c34b6

arch/arm64/include/asm/esr.h

+2 −1
Original line number Diff line number Diff line
@@ -43,7 +43,8 @@ 
#define ESR_ELx_EC_HVC64	(0x16)

#define ESR_ELx_EC_SMC64	(0x17)

#define ESR_ELx_EC_SYS64	(0x18)

/* Unallocated EC: 0x19 - 0x1E */

#define ESR_ELx_EC_SVE		(0x19)

/* Unallocated EC: 0x1A - 0x1E */

#define ESR_ELx_EC_IMP_DEF	(0x1f)

#define ESR_ELx_EC_IABT_LOW	(0x20)

#define ESR_ELx_EC_IABT_CUR	(0x21)

arch/arm64/include/asm/kvm_arm.h

+1 −0
Original line number Diff line number Diff line
@@ -187,6 +187,7 @@ 
#define CPTR_EL2_TCPAC	(1 << 31)

#define CPTR_EL2_TTA	(1 << 20)

#define CPTR_EL2_TFP	(1 << CPTR_EL2_TFP_SHIFT)

#define CPTR_EL2_TZ	(1 << 8)

#define CPTR_EL2_DEFAULT	0x000033ff



/* Hyp Debug Configuration Register bits */

arch/arm64/include/asm/sysreg.h

+21 −0
Original line number Diff line number Diff line
@@ -145,6 +145,7 @@ 


#define SYS_ID_AA64PFR0_EL1		sys_reg(3, 0, 0, 4, 0)

#define SYS_ID_AA64PFR1_EL1		sys_reg(3, 0, 0, 4, 1)

#define SYS_ID_AA64ZFR0_EL1		sys_reg(3, 0, 0, 4, 4)



#define SYS_ID_AA64DFR0_EL1		sys_reg(3, 0, 0, 5, 0)

#define SYS_ID_AA64DFR1_EL1		sys_reg(3, 0, 0, 5, 1)
@@ -160,6 +161,8 @@ 
#define SYS_ACTLR_EL1			sys_reg(3, 0, 1, 0, 1)

#define SYS_CPACR_EL1			sys_reg(3, 0, 1, 0, 2)



#define SYS_ZCR_EL1			sys_reg(3, 0, 1, 2, 0)



#define SYS_TTBR0_EL1			sys_reg(3, 0, 2, 0, 0)

#define SYS_TTBR1_EL1			sys_reg(3, 0, 2, 0, 1)

#define SYS_TCR_EL1			sys_reg(3, 0, 2, 0, 2)
@@ -250,6 +253,8 @@ 


#define SYS_PMCCFILTR_EL0		sys_reg (3, 3, 14, 15, 7)



#define SYS_ZCR_EL2			sys_reg(3, 4, 1, 2, 0)



#define SYS_DACR32_EL2			sys_reg(3, 4, 3, 0, 0)

#define SYS_IFSR32_EL2			sys_reg(3, 4, 5, 0, 1)

#define SYS_FPEXC32_EL2			sys_reg(3, 4, 5, 3, 0)
@@ -338,6 +343,7 @@ 
/* id_aa64pfr0 */

#define ID_AA64PFR0_CSV3_SHIFT		60

#define ID_AA64PFR0_CSV2_SHIFT		56

#define ID_AA64PFR0_SVE_SHIFT		32

#define ID_AA64PFR0_GIC_SHIFT		24

#define ID_AA64PFR0_ASIMD_SHIFT		20

#define ID_AA64PFR0_FP_SHIFT		16
@@ -346,6 +352,7 @@ 
#define ID_AA64PFR0_EL1_SHIFT		4

#define ID_AA64PFR0_EL0_SHIFT		0



#define ID_AA64PFR0_SVE			0x1

#define ID_AA64PFR0_FP_NI		0xf

#define ID_AA64PFR0_FP_SUPPORTED	0x0

#define ID_AA64PFR0_ASIMD_NI		0xf
@@ -447,6 +454,20 @@ 
#endif





/*

 * The ZCR_ELx_LEN_* definitions intentionally include bits [8:4] which

 * are reserved by the SVE architecture for future expansion of the LEN

 * field, with compatible semantics.

 */

#define ZCR_ELx_LEN_SHIFT	0

#define ZCR_ELx_LEN_SIZE	9

#define ZCR_ELx_LEN_MASK	0x1ff



#define CPACR_EL1_ZEN_EL1EN	(1 << 16) /* enable EL1 access */

#define CPACR_EL1_ZEN_EL0EN	(1 << 17) /* enable EL0 access, if EL1EN set */

#define CPACR_EL1_ZEN		(CPACR_EL1_ZEN_EL1EN | CPACR_EL1_ZEN_EL0EN)





/* Safe value for MPIDR_EL1: Bit31:RES1, Bit30:U:0, Bit24:MT:0 */

#define SYS_MPIDR_SAFE_VAL		(1UL << 31)

arch/arm64/kernel/traps.c

+1 −0
Original line number Diff line number Diff line
@@ -699,6 +699,7 @@ static const char *esr_class_str[] = { 
	[ESR_ELx_EC_HVC64]		= "HVC (AArch64)",

	[ESR_ELx_EC_SMC64]		= "SMC (AArch64)",

	[ESR_ELx_EC_SYS64]		= "MSR/MRS (AArch64)",

	[ESR_ELx_EC_SVE]		= "SVE",

	[ESR_ELx_EC_IMP_DEF]		= "EL3 IMP DEF",

	[ESR_ELx_EC_IABT_LOW]		= "IABT (lower EL)",

	[ESR_ELx_EC_IABT_CUR]		= "IABT (current EL)",