Loading drivers/clk/qcom/gcc-sm6150.c +15 −1 Original line number Diff line number Diff line Loading @@ -299,6 +299,8 @@ static struct clk_rcg2 gcc_cpuss_ahb_clk_src = { }; static const struct freq_tbl ftbl_gcc_emac_ptp_clk_src[] = { F(19200000, P_BI_TCXO, 1, 0, 0), F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0), F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0), F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0), Loading @@ -325,12 +327,24 @@ static struct clk_rcg2 gcc_emac_ptp_clk_src = { }, }; static const struct freq_tbl ftbl_gcc_emac_rgmii_clk_src[] = { F(2500000, P_BI_TCXO, 1, 25, 192), F(5000000, P_BI_TCXO, 1, 25, 96), F(19200000, P_BI_TCXO, 1, 0, 0), F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0), F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0), F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0), F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0), { } }; static struct clk_rcg2 gcc_emac_rgmii_clk_src = { .cmd_rcgr = 0x601c, .mnd_width = 8, .hid_width = 5, .parent_map = gcc_parent_map_6, .freq_tbl = ftbl_gcc_emac_ptp_clk_src, .freq_tbl = ftbl_gcc_emac_rgmii_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_emac_rgmii_clk_src", .parent_names = gcc_parent_names_6, Loading Loading
drivers/clk/qcom/gcc-sm6150.c +15 −1 Original line number Diff line number Diff line Loading @@ -299,6 +299,8 @@ static struct clk_rcg2 gcc_cpuss_ahb_clk_src = { }; static const struct freq_tbl ftbl_gcc_emac_ptp_clk_src[] = { F(19200000, P_BI_TCXO, 1, 0, 0), F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0), F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0), F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0), Loading @@ -325,12 +327,24 @@ static struct clk_rcg2 gcc_emac_ptp_clk_src = { }, }; static const struct freq_tbl ftbl_gcc_emac_rgmii_clk_src[] = { F(2500000, P_BI_TCXO, 1, 25, 192), F(5000000, P_BI_TCXO, 1, 25, 96), F(19200000, P_BI_TCXO, 1, 0, 0), F(25000000, P_GPLL0_OUT_AUX2, 12, 0, 0), F(50000000, P_GPLL0_OUT_AUX2, 6, 0, 0), F(75000000, P_GPLL0_OUT_AUX2, 4, 0, 0), F(125000000, P_GPLL7_OUT_MAIN, 4, 0, 0), F(250000000, P_GPLL7_OUT_MAIN, 2, 0, 0), { } }; static struct clk_rcg2 gcc_emac_rgmii_clk_src = { .cmd_rcgr = 0x601c, .mnd_width = 8, .hid_width = 5, .parent_map = gcc_parent_map_6, .freq_tbl = ftbl_gcc_emac_ptp_clk_src, .freq_tbl = ftbl_gcc_emac_rgmii_clk_src, .clkr.hw.init = &(struct clk_init_data){ .name = "gcc_emac_rgmii_clk_src", .parent_names = gcc_parent_names_6, Loading