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Commit 3fd76de2 authored by qctecmdr Service's avatar qctecmdr Service Committed by Gerrit - the friendly Code Review server
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Merge "clk: qcom: mdss: Program the DP PHY to enable all the DP lanes"

parents bb556d18 3527226f

drivers/clk/qcom/mdss/mdss-dp-pll-14nm.c

+17 −43
Original line number Diff line number Diff line
@@ -292,6 +292,7 @@ static int dp_vco_pll_init_db_14nm(struct dp_pll_db *pdb, 
		pdb->lock_cmp2_mode0 = 0x21;

		pdb->lock_cmp3_mode0 = 0x00;

		pdb->phy_vco_div = 0x1;

		pdb->lane_mode_1 = 0xc6;

		break;

	case DP_VCO_HSCLK_RATE_2700MHZDIV1000:

		pdb->hsclk_sel = 0x24;
@@ -303,6 +304,7 @@ static int dp_vco_pll_init_db_14nm(struct dp_pll_db *pdb, 
		pdb->lock_cmp2_mode0 = 0x38;

		pdb->lock_cmp3_mode0 = 0x00;

		pdb->phy_vco_div = 0x1;

		pdb->lane_mode_1 = 0xc4;

		break;

	case DP_VCO_HSCLK_RATE_5400MHZDIV1000:

		pdb->hsclk_sel = 0x20;
@@ -314,6 +316,7 @@ static int dp_vco_pll_init_db_14nm(struct dp_pll_db *pdb, 
		pdb->lock_cmp2_mode0 = 0x70;

		pdb->lock_cmp3_mode0 = 0x00;

		pdb->phy_vco_div = 0x2;

		pdb->lane_mode_1 = 0xc4;

		break;

	default:

		return -EINVAL;
@@ -334,17 +337,7 @@ int dp_config_vco_rate_14nm(struct dp_pll_vco_clk *vco, 
		return res;

	}



	if (pdb->lane_cnt != 4) {

		if (pdb->orientation == ORIENTATION_CC2)

			MDSS_PLL_REG_W(dp_res->phy_base,

				DP_PHY_PD_CTL, 0x2d);

		else

			MDSS_PLL_REG_W(dp_res->phy_base,

				DP_PHY_PD_CTL, 0x35);

	} else {

		MDSS_PLL_REG_W(dp_res->phy_base,

			DP_PHY_PD_CTL, 0x3d);

	}

	MDSS_PLL_REG_W(dp_res->phy_base, DP_PHY_PD_CTL, 0x3d);



	/* Make sure the PHY register writes are done */

	wmb();
@@ -418,6 +411,11 @@ int dp_config_vco_rate_14nm(struct dp_pll_vco_clk *vco, 
		QSERDES_COM_CORE_CLK_EN, 0x0f);

	wmb(); /* make sure write happens */



	MDSS_PLL_REG_W(dp_res->phy_base,

		QSERDES_TX0_OFFSET + TXn_LANE_MODE_1, pdb->lane_mode_1);

	MDSS_PLL_REG_W(dp_res->phy_base,

		QSERDES_TX1_OFFSET + TXn_LANE_MODE_1, pdb->lane_mode_1);



	if (pdb->orientation == ORIENTATION_CC2)

		MDSS_PLL_REG_W(dp_res->phy_base, DP_PHY_MODE, 0xc8);

	else
@@ -546,10 +544,8 @@ static bool dp_14nm_phy_rdy_status(struct mdss_pll_resources *dp_res) 
static int dp_pll_enable_14nm(struct clk_hw *hw)

{

	int rc = 0;

	u32 bias_en, drvr_en;

	struct dp_pll_vco_clk *vco = to_dp_vco_hw(hw);

	struct mdss_pll_resources *dp_res = vco->priv;

	struct dp_pll_db *pdb = (struct dp_pll_db *)dp_res->priv;



	MDSS_PLL_REG_W(dp_res->phy_base, DP_PHY_CFG, 0x01);

	MDSS_PLL_REG_W(dp_res->phy_base, DP_PHY_CFG, 0x05);
@@ -580,36 +576,14 @@ static int dp_pll_enable_14nm(struct clk_hw *hw) 


	pr_debug("PLL is locked\n");



	if (pdb->lane_cnt == 1) {

		bias_en = 0x3e;

		drvr_en = 0x13;

	} else {

		bias_en = 0x3f;

		drvr_en = 0x10;

	}



	if (pdb->lane_cnt != 4) {

		if (pdb->orientation == ORIENTATION_CC1) {

	MDSS_PLL_REG_W(dp_res->phy_base,

			QSERDES_TX1_OFFSET + TXn_TRANSCEIVER_BIAS_EN, bias_en);

		QSERDES_TX0_OFFSET + TXn_TRANSCEIVER_BIAS_EN, 0x3f);

	MDSS_PLL_REG_W(dp_res->phy_base,

			QSERDES_TX1_OFFSET + TXn_HIGHZ_DRVR_EN, drvr_en);

		} else {

		QSERDES_TX0_OFFSET + TXn_HIGHZ_DRVR_EN, 0x10);

	MDSS_PLL_REG_W(dp_res->phy_base,

			QSERDES_TX0_OFFSET + TXn_TRANSCEIVER_BIAS_EN, bias_en);

		QSERDES_TX1_OFFSET + TXn_TRANSCEIVER_BIAS_EN, 0x3f);

	MDSS_PLL_REG_W(dp_res->phy_base,

			QSERDES_TX0_OFFSET + TXn_HIGHZ_DRVR_EN, drvr_en);

		}

	} else {

		MDSS_PLL_REG_W(dp_res->phy_base,

			QSERDES_TX0_OFFSET + TXn_TRANSCEIVER_BIAS_EN, bias_en);

		MDSS_PLL_REG_W(dp_res->phy_base,

			QSERDES_TX0_OFFSET + TXn_HIGHZ_DRVR_EN, drvr_en);

		MDSS_PLL_REG_W(dp_res->phy_base,

			QSERDES_TX1_OFFSET + TXn_TRANSCEIVER_BIAS_EN, bias_en);

		MDSS_PLL_REG_W(dp_res->phy_base,

			QSERDES_TX1_OFFSET + TXn_HIGHZ_DRVR_EN, drvr_en);

	}

		QSERDES_TX1_OFFSET + TXn_HIGHZ_DRVR_EN, 0x10);



	MDSS_PLL_REG_W(dp_res->phy_base,

		QSERDES_TX0_OFFSET + TXn_TX_POL_INV, 0x0a);

drivers/clk/qcom/mdss/mdss-dp-pll-14nm.h

+3 −0
Original line number Diff line number Diff line
@@ -176,6 +176,9 @@ struct dp_pll_db { 


	/* PHY vco divider */

	u32 phy_vco_div;



	/* TX settings */

	u32 lane_mode_1;

};



int dp_vco_set_rate_14nm(struct clk_hw *hw, unsigned long rate,