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Commit 3527226f authored by Sankeerth Billakanti's avatar Sankeerth Billakanti
Browse files

clk: qcom: mdss: Program the DP PHY to enable all the DP lanes 



All the DP lanes are not getting powered on during link training.
This is happening because of the swapped lane mapping in sm6150
target. Adding changes to power on all the lanes of DP PHY.

Change-Id: I9b39011a6d11ded5fd29d300254a938630eb185f
Signed-off-by: default avatarSankeerth Billakanti <sbillaka@codeaurora.org>
parent de9012a8

drivers/clk/qcom/mdss/mdss-dp-pll-14nm.c

+9 −43
Original line number Diff line number Diff line
@@ -337,17 +337,7 @@ int dp_config_vco_rate_14nm(struct dp_pll_vco_clk *vco, 
		return res;

	}



	if (pdb->lane_cnt != 4) {

		if (pdb->orientation == ORIENTATION_CC2)

			MDSS_PLL_REG_W(dp_res->phy_base,

				DP_PHY_PD_CTL, 0x2d);

		else

			MDSS_PLL_REG_W(dp_res->phy_base,

				DP_PHY_PD_CTL, 0x35);

	} else {

		MDSS_PLL_REG_W(dp_res->phy_base,

			DP_PHY_PD_CTL, 0x3d);

	}

	MDSS_PLL_REG_W(dp_res->phy_base, DP_PHY_PD_CTL, 0x3d);



	/* Make sure the PHY register writes are done */

	wmb();
@@ -554,10 +544,8 @@ static bool dp_14nm_phy_rdy_status(struct mdss_pll_resources *dp_res) 
static int dp_pll_enable_14nm(struct clk_hw *hw)

{

	int rc = 0;

	u32 bias_en, drvr_en;

	struct dp_pll_vco_clk *vco = to_dp_vco_hw(hw);

	struct mdss_pll_resources *dp_res = vco->priv;

	struct dp_pll_db *pdb = (struct dp_pll_db *)dp_res->priv;



	MDSS_PLL_REG_W(dp_res->phy_base, DP_PHY_CFG, 0x01);

	MDSS_PLL_REG_W(dp_res->phy_base, DP_PHY_CFG, 0x05);
@@ -588,36 +576,14 @@ static int dp_pll_enable_14nm(struct clk_hw *hw) 


	pr_debug("PLL is locked\n");



	if (pdb->lane_cnt == 1) {

		bias_en = 0x3e;

		drvr_en = 0x13;

	} else {

		bias_en = 0x3f;

		drvr_en = 0x10;

	}



	if (pdb->lane_cnt != 4) {

		if (pdb->orientation == ORIENTATION_CC1) {

			MDSS_PLL_REG_W(dp_res->phy_base,

			QSERDES_TX1_OFFSET + TXn_TRANSCEIVER_BIAS_EN, bias_en);

	MDSS_PLL_REG_W(dp_res->phy_base,

			QSERDES_TX1_OFFSET + TXn_HIGHZ_DRVR_EN, drvr_en);

		} else {

		QSERDES_TX0_OFFSET + TXn_TRANSCEIVER_BIAS_EN, 0x3f);

	MDSS_PLL_REG_W(dp_res->phy_base,

			QSERDES_TX0_OFFSET + TXn_TRANSCEIVER_BIAS_EN, bias_en);

		QSERDES_TX0_OFFSET + TXn_HIGHZ_DRVR_EN, 0x10);

	MDSS_PLL_REG_W(dp_res->phy_base,

			QSERDES_TX0_OFFSET + TXn_HIGHZ_DRVR_EN, drvr_en);

		}

	} else {

		QSERDES_TX1_OFFSET + TXn_TRANSCEIVER_BIAS_EN, 0x3f);

	MDSS_PLL_REG_W(dp_res->phy_base,

			QSERDES_TX0_OFFSET + TXn_TRANSCEIVER_BIAS_EN, bias_en);

		MDSS_PLL_REG_W(dp_res->phy_base,

			QSERDES_TX0_OFFSET + TXn_HIGHZ_DRVR_EN, drvr_en);

		MDSS_PLL_REG_W(dp_res->phy_base,

			QSERDES_TX1_OFFSET + TXn_TRANSCEIVER_BIAS_EN, bias_en);

		MDSS_PLL_REG_W(dp_res->phy_base,

			QSERDES_TX1_OFFSET + TXn_HIGHZ_DRVR_EN, drvr_en);

	}

		QSERDES_TX1_OFFSET + TXn_HIGHZ_DRVR_EN, 0x10);



	MDSS_PLL_REG_W(dp_res->phy_base,

		QSERDES_TX0_OFFSET + TXn_TX_POL_INV, 0x0a);