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Commit de9012a8 authored by Sankeerth Billakanti's avatar Sankeerth Billakanti
Browse files

clk: qcom: mdss: Program the lane mode according to the specification 



Program the lane mode register with the relevant data for 1.62GHz,
2.7GHz and 5.4 GHz according to the platform specification for SM6150
DP PLL.

Change-Id: I13780ae1e9efa8184dcea3eb1d9a91cbf2b78cdd
Signed-off-by: default avatarSankeerth Billakanti <sbillaka@codeaurora.org>
parent e89a5466

drivers/clk/qcom/mdss/mdss-dp-pll-14nm.c

+8 −0
Original line number Diff line number Diff line
@@ -292,6 +292,7 @@ static int dp_vco_pll_init_db_14nm(struct dp_pll_db *pdb, 
		pdb->lock_cmp2_mode0 = 0x21;

		pdb->lock_cmp3_mode0 = 0x00;

		pdb->phy_vco_div = 0x1;

		pdb->lane_mode_1 = 0xc6;

		break;

	case DP_VCO_HSCLK_RATE_2700MHZDIV1000:

		pdb->hsclk_sel = 0x24;
@@ -303,6 +304,7 @@ static int dp_vco_pll_init_db_14nm(struct dp_pll_db *pdb, 
		pdb->lock_cmp2_mode0 = 0x38;

		pdb->lock_cmp3_mode0 = 0x00;

		pdb->phy_vco_div = 0x1;

		pdb->lane_mode_1 = 0xc4;

		break;

	case DP_VCO_HSCLK_RATE_5400MHZDIV1000:

		pdb->hsclk_sel = 0x20;
@@ -314,6 +316,7 @@ static int dp_vco_pll_init_db_14nm(struct dp_pll_db *pdb, 
		pdb->lock_cmp2_mode0 = 0x70;

		pdb->lock_cmp3_mode0 = 0x00;

		pdb->phy_vco_div = 0x2;

		pdb->lane_mode_1 = 0xc4;

		break;

	default:

		return -EINVAL;
@@ -418,6 +421,11 @@ int dp_config_vco_rate_14nm(struct dp_pll_vco_clk *vco, 
		QSERDES_COM_CORE_CLK_EN, 0x0f);

	wmb(); /* make sure write happens */



	MDSS_PLL_REG_W(dp_res->phy_base,

		QSERDES_TX0_OFFSET + TXn_LANE_MODE_1, pdb->lane_mode_1);

	MDSS_PLL_REG_W(dp_res->phy_base,

		QSERDES_TX1_OFFSET + TXn_LANE_MODE_1, pdb->lane_mode_1);



	if (pdb->orientation == ORIENTATION_CC2)

		MDSS_PLL_REG_W(dp_res->phy_base, DP_PHY_MODE, 0xc8);

	else

drivers/clk/qcom/mdss/mdss-dp-pll-14nm.h

+3 −0
Original line number Diff line number Diff line
@@ -176,6 +176,9 @@ struct dp_pll_db { 


	/* PHY vco divider */

	u32 phy_vco_div;



	/* TX settings */

	u32 lane_mode_1;

};



int dp_vco_set_rate_14nm(struct clk_hw *hw, unsigned long rate,