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Commit 3ea12806 authored by Will Deacon's avatar Will Deacon
Browse files

ARM: barrier: allow options to be passed to memory barrier instructions 



On ARMv7, the memory barrier instructions take an optional `option'
field which can be used to constrain the effects of a memory barrier
based on shareability and access type.

This patch allows the caller to pass these options if required, and
updates the smp_*() barriers to request inner-shareable barriers,
affecting only stores for the _wmb variant. wmb() is also changed to
use the -st version of dsb.

Reported-by: default avatarAlbin Tonnerre <albin.tonnerre@arm.com>
Reviewed-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
Signed-off-by: default avatarWill Deacon <will.deacon@arm.com>
parent 2c813980

arch/arm/include/asm/assembler.h

+2 −2
Original line number Diff line number Diff line
@@ -220,9 +220,9 @@ 
#ifdef CONFIG_SMP

#if __LINUX_ARM_ARCH__ >= 7

	.ifeqs "\mode","arm"

	ALT_SMP(dmb)

	ALT_SMP(dmb	ish)

	.else

	ALT_SMP(W(dmb))

	ALT_SMP(W(dmb)	ish)

	.endif

#elif __LINUX_ARM_ARCH__ == 6

	ALT_SMP(mcr	p15, 0, r0, c7, c10, 5)	@ dmb

arch/arm/include/asm/barrier.h

+16 −16
Original line number Diff line number Diff line
@@ -14,27 +14,27 @@ 
#endif



#if __LINUX_ARM_ARCH__ >= 7

#define isb() __asm__ __volatile__ ("isb" : : : "memory")

#define dsb() __asm__ __volatile__ ("dsb" : : : "memory")

#define dmb() __asm__ __volatile__ ("dmb" : : : "memory")

#define isb(option) __asm__ __volatile__ ("isb " #option : : : "memory")

#define dsb(option) __asm__ __volatile__ ("dsb " #option : : : "memory")

#define dmb(option) __asm__ __volatile__ ("dmb " #option : : : "memory")

#elif defined(CONFIG_CPU_XSC3) || __LINUX_ARM_ARCH__ == 6

#define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \

#define isb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \

				    : : "r" (0) : "memory")

#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \

#define dsb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \

				    : : "r" (0) : "memory")

#define dmb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \

#define dmb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 5" \

				    : : "r" (0) : "memory")

#elif defined(CONFIG_CPU_FA526)

#define isb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \

#define isb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c5, 4" \

				    : : "r" (0) : "memory")

#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \

#define dsb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \

				    : : "r" (0) : "memory")

#define dmb() __asm__ __volatile__ ("" : : : "memory")

#define dmb(x) __asm__ __volatile__ ("" : : : "memory")

#else

#define isb() __asm__ __volatile__ ("" : : : "memory")

#define dsb() __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \

#define isb(x) __asm__ __volatile__ ("" : : : "memory")

#define dsb(x) __asm__ __volatile__ ("mcr p15, 0, %0, c7, c10, 4" \

				    : : "r" (0) : "memory")

#define dmb() __asm__ __volatile__ ("" : : : "memory")

#define dmb(x) __asm__ __volatile__ ("" : : : "memory")

#endif



#ifdef CONFIG_ARCH_HAS_BARRIERS
@@ -42,7 +42,7 @@ 
#elif defined(CONFIG_ARM_DMA_MEM_BUFFERABLE) || defined(CONFIG_SMP)

#define mb()		do { dsb(); outer_sync(); } while (0)

#define rmb()		dsb()

#define wmb()		mb()

#define wmb()		do { dsb(st); outer_sync(); } while (0)

#else

#define mb()		barrier()

#define rmb()		barrier()
@@ -54,9 +54,9 @@ 
#define smp_rmb()	barrier()

#define smp_wmb()	barrier()

#else

#define smp_mb()	dmb()

#define smp_rmb()	dmb()

#define smp_wmb()	dmb()

#define smp_mb()	dmb(ish)

#define smp_rmb()	smp_mb()

#define smp_wmb()	dmb(ishst)

#endif



#define read_barrier_depends()		do { } while(0)